/* Autogenerated file, DO NOT EDIT manually! generated by gen_perf.py * * Copyright (c) 2015 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include #include "util/hash_table.h" #include "gen_perf_metrics.h" #include "perf/gen_perf.h" #define MIN(a, b) ((a < b) ? (a) : (b)) #define MAX(a, b) ((a > b) ? (a) : (b)) /* Render Metrics Basic Gen7.5 :: GPU Core Clocks */ static uint64_t hsw__render_basic__gpu_core_clocks__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ */ uint64_t tmp0 = accumulator[query->c_offset + 2]; return tmp0; } /* Render Metrics Basic Gen7.5 :: EU Active */ static float hsw__render_basic__eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 0]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: TES EU Stall */ static float hsw__render_basic__ds_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: Alpha Test Fails */ static uint64_t hsw__render_basic__alpha_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 37 READ */ uint64_t tmp0 = accumulator[query->a_offset + 37]; return tmp0; } /* Render Metrics Basic Gen7.5 :: Sampler 1 Bottleneck */ static float hsw__render_basic__sampler1_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen7.5 :: TES Threads Dispatched */ static uint64_t hsw__render_basic__ds_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 15 READ */ uint64_t tmp0 = accumulator[query->a_offset + 15]; return tmp0; } /* Render Metrics Basic Gen7.5 :: TES AVG Active per Thread */ static uint64_t hsw__render_basic__ds_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ $DsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__ds_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: GS Threads Dispatched */ static uint64_t hsw__render_basic__gs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 25 READ */ uint64_t tmp0 = accumulator[query->a_offset + 25]; return tmp0; } /* Render Metrics Basic Gen7.5 :: GS EU Stall */ static float hsw__render_basic__gs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 23]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: CS EU Active */ static float hsw__render_basic__cs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: VS EU Active */ static float hsw__render_basic__vs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 2]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: TCS EU Active */ static float hsw__render_basic__hs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: TES EU Active */ static float hsw__render_basic__ds_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: GS EU Active */ static float hsw__render_basic__gs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: FS EU Active */ static float hsw__render_basic__ps_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: CS EU Stall */ static float hsw__render_basic__cs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 18]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: EU Stall */ static float hsw__render_basic__eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 1]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: VS EU Stall */ static float hsw__render_basic__vs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 3]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: TCS EU Stall */ static float hsw__render_basic__hs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: FS EU Stall */ static float hsw__render_basic__ps_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 28]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen7.5 :: GPU Time Elapsed */ static uint64_t hsw__render_basic__gpu_time__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV */ uint64_t tmp0 = accumulator[query->gpu_time_offset + 0]; uint64_t tmp1 = tmp0 * 1000000000; uint64_t tmp2 = tmp1; uint64_t tmp3 = perf->sys_vars.timestamp_frequency; uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen7.5 :: CS Duration */ static uint64_t hsw__render_basic__cs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 18 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 18]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Render Metrics Basic Gen7.5 :: VS Threads Dispatched */ static uint64_t hsw__render_basic__vs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 5 READ */ uint64_t tmp0 = accumulator[query->a_offset + 5]; return tmp0; } /* Render Metrics Basic Gen7.5 :: FS Threads Dispatched */ static uint64_t hsw__render_basic__ps_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 30 READ */ uint64_t tmp0 = accumulator[query->a_offset + 30]; return tmp0; } /* Render Metrics Basic Gen7.5 :: Sampler 0 Busy */ static float hsw__render_basic__sampler0_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen7.5 :: Sampler 1 Busy */ static float hsw__render_basic__sampler1_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 1 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen7.5 :: Samplers Busy */ static float hsw__render_basic__samplers_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ UADD $GpuCoreClocks FDIV 2 FDIV 100 FMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; double tmp3 = tmp2; double tmp4 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp5 = tmp4 ? tmp3 / tmp4 : 0; double tmp6 = tmp5; double tmp7 = 2; double tmp8 = tmp7 ? tmp6 / tmp7 : 0; double tmp9 = tmp8 * 100; return tmp9; } /* Render Metrics Basic Gen7.5 :: TES Duration */ static uint64_t hsw__render_basic__ds_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 13 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 13]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Render Metrics Basic Gen7.5 :: GTI Fixed Pipe Throughput */ static uint64_t hsw__render_basic__gti_vf_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen7.5 :: GTI Read Throughput */ static uint64_t hsw__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ 128 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = tmp0 * 128; return tmp1; } /* Render Metrics Basic Gen7.5 :: CS Threads Dispatched */ static uint64_t hsw__render_basic__cs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 20 READ */ uint64_t tmp0 = accumulator[query->a_offset + 20]; return tmp0; } /* Render Metrics Basic Gen7.5 :: CS AVG Active per Thread */ static uint64_t hsw__render_basic__cs_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ $CsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__cs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: Sampler 0 Bottleneck */ static float hsw__render_basic__sampler0_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen7.5 :: GS AVG Stall per Thread */ static uint64_t hsw__render_basic__gs_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 23 READ $GsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 23]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__gs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: Sampler 0 Texels LOD0 */ static uint64_t hsw__render_basic__sampler0_texels__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen7.5 :: Sampler 1 Texels LOD0 */ static uint64_t hsw__render_basic__sampler1_texels__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen7.5 :: Sampler Texels LOD0 */ static uint64_t hsw__render_basic__sampler_texels__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $Sampler0Texels $Sampler1Texels UADD $EuSlicesTotalCount UMUL */ uint64_t tmp0 = hsw__render_basic__sampler0_texels__read(perf, query, accumulator) + hsw__render_basic__sampler1_texels__read(perf, query, accumulator); uint64_t tmp1 = tmp0 * perf->sys_vars.n_eu_slices; return tmp1; } /* Render Metrics Basic Gen7.5 :: GS Duration */ static uint64_t hsw__render_basic__gs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 23 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 23]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Render Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ static uint64_t hsw__render_basic__avg_gpu_core_frequency__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ uint64_t tmp0 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * 1000000000; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ static uint64_t hsw__render_basic__avg_gpu_core_frequency__max(struct gen_perf *perf) { /* RPN equation: $GpuMaxFrequency */ return perf->sys_vars.gt_max_freq; } /* Render Metrics Basic Gen7.5 :: EU Idle */ static float hsw__render_basic__eu_idle__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 100 $EuActive $EuStall FADD FSUB */ double tmp0 = hsw__render_basic__eu_active__read(perf, query, accumulator) + hsw__render_basic__eu_stall__read(perf, query, accumulator); double tmp1 = 100 - tmp0; return tmp1; } /* Render Metrics Basic Gen7.5 :: GTI Depth Throughput */ static uint64_t hsw__render_basic__gti_depth_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen7.5 :: GTI Write Throughput */ static uint64_t hsw__render_basic__gti_write_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen7.5 :: FS AVG Stall per Thread */ static uint64_t hsw__render_basic__ps_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 28 READ $PsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 28]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__ps_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: GTI L3 Throughput */ static uint64_t hsw__render_basic__gti_l3_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen7.5 :: VS AVG Stall per Thread */ static uint64_t hsw__render_basic__vs_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 3 READ $VsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 3]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__vs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: Samples Blended */ static uint64_t hsw__render_basic__samples_blended__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ $EuSlicesTotalCount 4 UMUL UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = perf->sys_vars.n_eu_slices * 4; uint64_t tmp2 = tmp0 * tmp1; return tmp2; } /* Render Metrics Basic Gen7.5 :: GPU Busy */ static float hsw__render_basic__gpu_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 41]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen7.5 :: FS AVG Active per Thread */ static uint64_t hsw__render_basic__ps_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ $PsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__ps_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: Early Depth Test Fails */ static uint64_t hsw__render_basic__early_depth_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 35 READ */ uint64_t tmp0 = accumulator[query->a_offset + 35]; return tmp0; } /* Render Metrics Basic Gen7.5 :: TCS Duration */ static uint64_t hsw__render_basic__hs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 8 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 8]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Render Metrics Basic Gen7.5 :: TES AVG Stall per Thread */ static uint64_t hsw__render_basic__ds_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ $DsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__ds_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: GS AVG Active per Thread */ static uint64_t hsw__render_basic__gs_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ $GsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__gs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: TCS Threads Dispatched */ static uint64_t hsw__render_basic__hs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 10 READ */ uint64_t tmp0 = accumulator[query->a_offset + 10]; return tmp0; } /* Render Metrics Basic Gen7.5 :: TCS AVG Stall per Thread */ static uint64_t hsw__render_basic__hs_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ $HsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__hs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: Samples Killed in FS */ static uint64_t hsw__render_basic__samples_killed_in_ps__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 36 READ */ uint64_t tmp0 = accumulator[query->a_offset + 36]; return tmp0; } /* Render Metrics Basic Gen7.5 :: Late Depth Test Fails */ static uint64_t hsw__render_basic__post_ps_depth_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 39 READ $SamplesKilledInPs USUB */ uint64_t tmp0 = accumulator[query->a_offset + 39]; uint64_t tmp1 = tmp0 - hsw__render_basic__samples_killed_in_ps__read(perf, query, accumulator); return tmp1; } /* Render Metrics Basic Gen7.5 :: Sampler Bottleneck */ static float hsw__render_basic__sampler_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $Sampler0Bottleneck $Sampler1Bottleneck FMAX */ double tmp0 = hsw__render_basic__sampler0_bottleneck__read(perf, query, accumulator); double tmp1 = hsw__render_basic__sampler1_bottleneck__read(perf, query, accumulator); double tmp2 = MAX(tmp0, tmp1); return tmp2; } /* Render Metrics Basic Gen7.5 :: TCS AVG Active per Thread */ static uint64_t hsw__render_basic__hs_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ $HsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__hs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: FS Duration */ static uint64_t hsw__render_basic__ps_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 28 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 28]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Render Metrics Basic Gen7.5 :: Early Hi-Depth Test Fails */ static uint64_t hsw__render_basic__hi_depth_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 33 READ */ uint64_t tmp0 = accumulator[query->a_offset + 33]; return tmp0; } /* Render Metrics Basic Gen7.5 :: CS AVG Stall per Thread */ static uint64_t hsw__render_basic__cs_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 18 READ $CsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 18]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__cs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: Late Stencil Test Fails */ static uint64_t hsw__render_basic__post_ps_stencil_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 38 READ */ uint64_t tmp0 = accumulator[query->a_offset + 38]; return tmp0; } /* Render Metrics Basic Gen7.5 :: GTI RCC Throughput */ static uint64_t hsw__render_basic__gti_rcc_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen7.5 :: L3 Sampler Throughput */ static uint64_t hsw__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ B 7 READ UADD 2 UMUL $EuSlicesTotalCount UMUL 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = accumulator[query->b_offset + 7]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 2; uint64_t tmp4 = tmp3 * perf->sys_vars.n_eu_slices; uint64_t tmp5 = tmp4 * 64; return tmp5; } /* Render Metrics Basic Gen7.5 :: VS AVG Active per Thread */ static uint64_t hsw__render_basic__vs_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ $VsThreads UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 2]; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__render_basic__vs_threads__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen7.5 :: VS Duration */ static uint64_t hsw__render_basic__vs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 3 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 2]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 3]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Render Metrics Basic Gen7.5 :: Samples Written */ static uint64_t hsw__render_basic__samples_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 40 READ */ uint64_t tmp0 = accumulator[query->a_offset + 40]; return tmp0; } /* Compute Metrics Basic Gen7.5 :: GPU Core Clocks */ #define hsw__compute_basic__gpu_core_clocks__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen7.5 :: EU Active */ #define hsw__compute_basic__eu_active__read \ hsw__render_basic__eu_active__read /* Compute Metrics Basic Gen7.5 :: TES EU Stall */ #define hsw__compute_basic__ds_eu_stall__read \ hsw__render_basic__ds_eu_stall__read /* Compute Metrics Basic Gen7.5 :: Typed Bytes Written */ static uint64_t hsw__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ B 7 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = accumulator[query->b_offset + 7]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen7.5 :: Alpha Test Fails */ #define hsw__compute_basic__alpha_test_fails__read \ hsw__render_basic__alpha_test_fails__read /* Compute Metrics Basic Gen7.5 :: TCS Threads Dispatched */ #define hsw__compute_basic__hs_threads__read \ hsw__render_basic__hs_threads__read /* Compute Metrics Basic Gen7.5 :: TCS AVG Active per Thread */ #define hsw__compute_basic__hs_eu_active_per_thread__read \ hsw__render_basic__hs_eu_active_per_thread__read /* Compute Metrics Basic Gen7.5 :: GS Threads Dispatched */ #define hsw__compute_basic__gs_threads__read \ hsw__render_basic__gs_threads__read /* Compute Metrics Basic Gen7.5 :: GS EU Stall */ #define hsw__compute_basic__gs_eu_stall__read \ hsw__render_basic__gs_eu_stall__read /* Compute Metrics Basic Gen7.5 :: VS Threads Dispatched */ #define hsw__compute_basic__vs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen7.5 :: FS Threads Dispatched */ #define hsw__compute_basic__ps_threads__read \ hsw__render_basic__ps_threads__read /* Compute Metrics Basic Gen7.5 :: CS Threads Dispatched */ #define hsw__compute_basic__cs_threads__read \ hsw__render_basic__cs_threads__read /* Compute Metrics Basic Gen7.5 :: CS AVG Active per Thread */ #define hsw__compute_basic__cs_eu_active_per_thread__read \ hsw__render_basic__cs_eu_active_per_thread__read /* Compute Metrics Basic Gen7.5 :: Untyped Bytes Read */ static uint64_t hsw__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen7.5 :: GS AVG Stall per Thread */ #define hsw__compute_basic__gs_eu_stall_per_thread__read \ hsw__render_basic__gs_eu_stall_per_thread__read /* Compute Metrics Basic Gen7.5 :: Typed Atomics */ static uint64_t hsw__compute_basic__typed_atomics__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ C 1 READ UADD $EuSlicesTotalCount UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_slices; return tmp3; } /* Compute Metrics Basic Gen7.5 :: GPU Time Elapsed */ #define hsw__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ #define hsw__compute_basic__avg_gpu_core_frequency__read \ hsw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ #define hsw__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen7.5 :: SLM Bytes Read */ static uint64_t hsw__compute_basic__slm_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ C 7 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = accumulator[query->c_offset + 7]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen7.5 :: FS AVG Stall per Thread */ #define hsw__compute_basic__ps_eu_stall_per_thread__read \ hsw__render_basic__ps_eu_stall_per_thread__read /* Compute Metrics Basic Gen7.5 :: TES EU Active */ #define hsw__compute_basic__ds_eu_active__read \ hsw__render_basic__ds_eu_active__read /* Compute Metrics Basic Gen7.5 :: VS AVG Stall per Thread */ #define hsw__compute_basic__vs_eu_stall_per_thread__read \ hsw__render_basic__vs_eu_stall_per_thread__read /* Compute Metrics Basic Gen7.5 :: TCS EU Stall */ #define hsw__compute_basic__hs_eu_stall__read \ hsw__render_basic__hs_eu_stall__read /* Compute Metrics Basic Gen7.5 :: GPU Busy */ #define hsw__compute_basic__gpu_busy__read \ hsw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen7.5 :: FS AVG Active per Thread */ #define hsw__compute_basic__ps_eu_active_per_thread__read \ hsw__render_basic__ps_eu_active_per_thread__read /* Compute Metrics Basic Gen7.5 :: Early Depth Test Fails */ #define hsw__compute_basic__early_depth_test_fails__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen7.5 :: TES Threads Dispatched */ #define hsw__compute_basic__ds_threads__read \ hsw__render_basic__ds_threads__read /* Compute Metrics Basic Gen7.5 :: TES AVG Active per Thread */ #define hsw__compute_basic__ds_eu_active_per_thread__read \ hsw__render_basic__ds_eu_active_per_thread__read /* Compute Metrics Basic Gen7.5 :: GS EU Active */ #define hsw__compute_basic__gs_eu_active__read \ hsw__render_basic__gs_eu_active__read /* Compute Metrics Basic Gen7.5 :: FS EU Active */ #define hsw__compute_basic__ps_eu_active__read \ hsw__render_basic__ps_eu_active__read /* Compute Metrics Basic Gen7.5 :: TES AVG Stall per Thread */ #define hsw__compute_basic__ds_eu_stall_per_thread__read \ hsw__render_basic__ds_eu_stall_per_thread__read /* Compute Metrics Basic Gen7.5 :: GS AVG Active per Thread */ #define hsw__compute_basic__gs_eu_active_per_thread__read \ hsw__render_basic__gs_eu_active_per_thread__read /* Compute Metrics Basic Gen7.5 :: Untyped Writes */ static uint64_t hsw__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ B 3 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = accumulator[query->b_offset + 3]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen7.5 :: SLM Bytes Written */ static uint64_t hsw__compute_basic__slm_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ C 5 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = accumulator[query->c_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen7.5 :: TCS AVG Stall per Thread */ #define hsw__compute_basic__hs_eu_stall_per_thread__read \ hsw__render_basic__hs_eu_stall_per_thread__read /* Compute Metrics Basic Gen7.5 :: TCS EU Active */ #define hsw__compute_basic__hs_eu_active__read \ hsw__render_basic__hs_eu_active__read /* Compute Metrics Basic Gen7.5 :: Samples Killed in FS */ #define hsw__compute_basic__samples_killed_in_ps__read \ hsw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen7.5 :: Late Depth Test Fails */ #define hsw__compute_basic__post_ps_depth_test_fails__read \ hsw__render_basic__post_ps_depth_test_fails__read /* Compute Metrics Basic Gen7.5 :: FS EU Stall */ #define hsw__compute_basic__ps_eu_stall__read \ hsw__render_basic__ps_eu_stall__read /* Compute Metrics Basic Gen7.5 :: EU Stall */ #define hsw__compute_basic__eu_stall__read \ hsw__render_basic__eu_stall__read /* Compute Metrics Basic Gen7.5 :: Early Hi-Depth Test Fails */ #define hsw__compute_basic__hi_depth_test_fails__read \ hsw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen7.5 :: VS EU Active */ #define hsw__compute_basic__vs_eu_active__read \ hsw__render_basic__vs_eu_active__read /* Compute Metrics Basic Gen7.5 :: CS EU Active */ #define hsw__compute_basic__cs_eu_active__read \ hsw__render_basic__cs_eu_active__read /* Compute Metrics Basic Gen7.5 :: CS AVG Stall per Thread */ #define hsw__compute_basic__cs_eu_stall_per_thread__read \ hsw__render_basic__cs_eu_stall_per_thread__read /* Compute Metrics Basic Gen7.5 :: Late Stencil Test Fails */ #define hsw__compute_basic__post_ps_stencil_test_fails__read \ hsw__render_basic__post_ps_stencil_test_fails__read /* Compute Metrics Basic Gen7.5 :: VS AVG Active per Thread */ #define hsw__compute_basic__vs_eu_active_per_thread__read \ hsw__render_basic__vs_eu_active_per_thread__read /* Compute Metrics Basic Gen7.5 :: CS EU Stall */ #define hsw__compute_basic__cs_eu_stall__read \ hsw__render_basic__cs_eu_stall__read /* Compute Metrics Basic Gen7.5 :: Typed Bytes Read */ static uint64_t hsw__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen7.5 :: Samples Written */ #define hsw__compute_basic__samples_written__read \ hsw__render_basic__samples_written__read /* Compute Metrics Basic Gen7.5 :: VS EU Stall */ #define hsw__compute_basic__vs_eu_stall__read \ hsw__render_basic__vs_eu_stall__read /* Compute Metrics Extended Gen7.5 :: EuUntypedWrites0 */ static uint64_t hsw__compute_extended__eu_untyped_writes0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 1 READ */ uint64_t tmp0 = accumulator[query->b_offset + 1]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: Untyped Writes 0 */ static uint64_t hsw__compute_extended__untyped_writes0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ */ uint64_t tmp0 = accumulator[query->c_offset + 1]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: UntypedWritesPerCacheLine */ static float hsw__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuUntypedWrites0 $UntypedWrites0 FDIV */ double tmp0 = hsw__compute_extended__eu_untyped_writes0__read(perf, query, accumulator); double tmp1 = hsw__compute_extended__untyped_writes0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen7.5 :: Typed Reads 0 */ #define hsw__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen7.5 :: Typed Writes 0 */ static uint64_t hsw__compute_extended__typed_writes0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ */ uint64_t tmp0 = accumulator[query->c_offset + 0]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: EuTypedAtomics0 */ static uint64_t hsw__compute_extended__eu_typed_atomics0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ */ uint64_t tmp0 = accumulator[query->b_offset + 5]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: Typed Atomics 0 */ static uint64_t hsw__compute_extended__typed_atomics0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ */ uint64_t tmp0 = accumulator[query->c_offset + 4]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: TypedAtomicsPerCacheLine */ static float hsw__compute_extended__typed_atomics_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedAtomics0 $TypedAtomics0 FDIV */ double tmp0 = hsw__compute_extended__eu_typed_atomics0__read(perf, query, accumulator); double tmp1 = hsw__compute_extended__typed_atomics0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen7.5 :: EuUntypedReads0 */ static uint64_t hsw__compute_extended__eu_untyped_reads0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ */ uint64_t tmp0 = accumulator[query->b_offset + 0]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: EuUntypedAtomics0 */ static uint64_t hsw__compute_extended__eu_untyped_atomics0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ */ uint64_t tmp0 = accumulator[query->b_offset + 4]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: GPU Core Clocks */ static uint64_t hsw__compute_extended__gpu_clocks__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ */ uint64_t tmp0 = accumulator[query->b_offset + 7]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: CS Threads Dispatched */ #define hsw__compute_extended__cs_threads__read \ hsw__render_basic__cs_threads__read /* Compute Metrics Extended Gen7.5 :: EuTypedWrites0 */ static uint64_t hsw__compute_extended__eu_typed_writes0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ */ uint64_t tmp0 = accumulator[query->b_offset + 3]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: TypedWritesPerCacheLine */ static float hsw__compute_extended__typed_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedWrites0 $TypedWrites0 FDIV */ double tmp0 = hsw__compute_extended__eu_typed_writes0__read(perf, query, accumulator); double tmp1 = hsw__compute_extended__typed_writes0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen7.5 :: EuTypedReads0 */ static uint64_t hsw__compute_extended__eu_typed_reads0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ */ uint64_t tmp0 = accumulator[query->b_offset + 2]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: EuUrbAtomics0 */ static uint64_t hsw__compute_extended__eu_urb_atomics0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ */ uint64_t tmp0 = accumulator[query->b_offset + 6]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: Untyped Reads 0 */ static uint64_t hsw__compute_extended__untyped_reads0__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ */ uint64_t tmp0 = accumulator[query->c_offset + 3]; return tmp0; } /* Compute Metrics Extended Gen7.5 :: UntypedReadsPerCacheLine */ static float hsw__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuUntypedReads0 $UntypedReads0 FDIV */ double tmp0 = hsw__compute_extended__eu_untyped_reads0__read(perf, query, accumulator); double tmp1 = hsw__compute_extended__untyped_reads0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen7.5 :: GPU Time Elapsed */ #define hsw__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen7.5 :: TypedReadsPerCacheLine */ static float hsw__compute_extended__typed_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedReads0 $TypedReads0 FDIV */ double tmp0 = hsw__compute_extended__eu_typed_reads0__read(perf, query, accumulator); double tmp1 = hsw__compute_extended__typed_reads0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Memory Reads Distribution Gen7.5 :: GPU Core Clocks */ static uint64_t hsw__memory_reads__gpu_core_clocks__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ */ uint64_t tmp0 = accumulator[query->c_offset + 7]; return tmp0; } /* Memory Reads Distribution Gen7.5 :: EU Active */ static float hsw__memory_reads__eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 0]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: TES EU Stall */ static float hsw__memory_reads__ds_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: Alpha Test Fails */ #define hsw__memory_reads__alpha_test_fails__read \ hsw__render_basic__alpha_test_fails__read /* Memory Reads Distribution Gen7.5 :: TES Threads Dispatched */ #define hsw__memory_reads__ds_threads__read \ hsw__render_basic__ds_threads__read /* Memory Reads Distribution Gen7.5 :: TES AVG Active per Thread */ #define hsw__memory_reads__ds_eu_active_per_thread__read \ hsw__render_basic__ds_eu_active_per_thread__read /* Memory Reads Distribution Gen7.5 :: GS Threads Dispatched */ #define hsw__memory_reads__gs_threads__read \ hsw__render_basic__gs_threads__read /* Memory Reads Distribution Gen7.5 :: GS EU Stall */ static float hsw__memory_reads__gs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 23]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: VS Threads Dispatched */ #define hsw__memory_reads__vs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen7.5 :: LLC GPU Read Accesses */ static uint64_t hsw__memory_reads__llc_read_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ */ uint64_t tmp0 = accumulator[query->c_offset + 6]; return tmp0; } /* Memory Reads Distribution Gen7.5 :: FS Threads Dispatched */ #define hsw__memory_reads__ps_threads__read \ hsw__render_basic__ps_threads__read /* Memory Reads Distribution Gen7.5 :: GtiMemoryReads */ static uint64_t hsw__memory_reads__gti_memory_reads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ */ uint64_t tmp0 = accumulator[query->c_offset + 5]; return tmp0; } /* Memory Reads Distribution Gen7.5 :: CS Threads Dispatched */ #define hsw__memory_reads__cs_threads__read \ hsw__render_basic__cs_threads__read /* Memory Reads Distribution Gen7.5 :: CS AVG Active per Thread */ #define hsw__memory_reads__cs_eu_active_per_thread__read \ hsw__render_basic__cs_eu_active_per_thread__read /* Memory Reads Distribution Gen7.5 :: GtiRczMemoryReads */ #define hsw__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen7.5 :: GS AVG Stall per Thread */ #define hsw__memory_reads__gs_eu_stall_per_thread__read \ hsw__render_basic__gs_eu_stall_per_thread__read /* Memory Reads Distribution Gen7.5 :: GPU Time Elapsed */ #define hsw__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen7.5 :: AVG GPU Core Frequency */ static uint64_t hsw__memory_reads__avg_gpu_core_frequency__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ uint64_t tmp0 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator) * 1000000000; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__memory_reads__gpu_time__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Memory Reads Distribution Gen7.5 :: AVG GPU Core Frequency */ #define hsw__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen7.5 :: GtiRccMemoryReads */ #define hsw__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen7.5 :: FS AVG Stall per Thread */ #define hsw__memory_reads__ps_eu_stall_per_thread__read \ hsw__render_basic__ps_eu_stall_per_thread__read /* Memory Reads Distribution Gen7.5 :: TES EU Active */ static float hsw__memory_reads__ds_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: VS AVG Stall per Thread */ #define hsw__memory_reads__vs_eu_stall_per_thread__read \ hsw__render_basic__vs_eu_stall_per_thread__read /* Memory Reads Distribution Gen7.5 :: TCS EU Stall */ static float hsw__memory_reads__hs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: GPU Busy */ static float hsw__memory_reads__gpu_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 41]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Memory Reads Distribution Gen7.5 :: FS AVG Active per Thread */ #define hsw__memory_reads__ps_eu_active_per_thread__read \ hsw__render_basic__ps_eu_active_per_thread__read /* Memory Reads Distribution Gen7.5 :: GtiCmdStreamerMemoryReads */ #define hsw__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen7.5 :: Early Depth Test Fails */ #define hsw__memory_reads__early_depth_test_fails__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen7.5 :: GS EU Active */ static float hsw__memory_reads__gs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: FS EU Active */ static float hsw__memory_reads__ps_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: TES AVG Stall per Thread */ #define hsw__memory_reads__ds_eu_stall_per_thread__read \ hsw__render_basic__ds_eu_stall_per_thread__read /* Memory Reads Distribution Gen7.5 :: GS AVG Active per Thread */ #define hsw__memory_reads__gs_eu_active_per_thread__read \ hsw__render_basic__gs_eu_active_per_thread__read /* Memory Reads Distribution Gen7.5 :: GtiHiDepthMemoryReads */ #define hsw__memory_reads__gti_hi_depth_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen7.5 :: TCS Threads Dispatched */ #define hsw__memory_reads__hs_threads__read \ hsw__render_basic__hs_threads__read /* Memory Reads Distribution Gen7.5 :: TCS AVG Stall per Thread */ #define hsw__memory_reads__hs_eu_stall_per_thread__read \ hsw__render_basic__hs_eu_stall_per_thread__read /* Memory Reads Distribution Gen7.5 :: TCS EU Active */ static float hsw__memory_reads__hs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: Samples Killed in FS */ #define hsw__memory_reads__samples_killed_in_ps__read \ hsw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen7.5 :: Late Depth Test Fails */ #define hsw__memory_reads__post_ps_depth_test_fails__read \ hsw__render_basic__post_ps_depth_test_fails__read /* Memory Reads Distribution Gen7.5 :: TCS AVG Active per Thread */ #define hsw__memory_reads__hs_eu_active_per_thread__read \ hsw__render_basic__hs_eu_active_per_thread__read /* Memory Reads Distribution Gen7.5 :: FS EU Stall */ static float hsw__memory_reads__ps_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 28]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: EU Stall */ static float hsw__memory_reads__eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 1]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: GtiMscMemoryReads */ #define hsw__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen7.5 :: Early Hi-Depth Test Fails */ #define hsw__memory_reads__hi_depth_test_fails__read \ hsw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen7.5 :: VS EU Active */ static float hsw__memory_reads__vs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 2]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: CS EU Active */ static float hsw__memory_reads__cs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: CS AVG Stall per Thread */ #define hsw__memory_reads__cs_eu_stall_per_thread__read \ hsw__render_basic__cs_eu_stall_per_thread__read /* Memory Reads Distribution Gen7.5 :: GtiVfMemoryReads */ #define hsw__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen7.5 :: Late Stencil Test Fails */ #define hsw__memory_reads__post_ps_stencil_test_fails__read \ hsw__render_basic__post_ps_stencil_test_fails__read /* Memory Reads Distribution Gen7.5 :: GtiStcMemoryReads */ #define hsw__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen7.5 :: VS AVG Active per Thread */ #define hsw__memory_reads__vs_eu_active_per_thread__read \ hsw__render_basic__vs_eu_active_per_thread__read /* Memory Reads Distribution Gen7.5 :: GtiRsMemoryReads */ #define hsw__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen7.5 :: CS EU Stall */ static float hsw__memory_reads__cs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 18]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Reads Distribution Gen7.5 :: Samples Written */ #define hsw__memory_reads__samples_written__read \ hsw__render_basic__samples_written__read /* Memory Reads Distribution Gen7.5 :: GtiL3Reads */ #define hsw__memory_reads__gti_l3_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen7.5 :: VS EU Stall */ static float hsw__memory_reads__vs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 3]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__memory_reads__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Memory Writes Distribution Gen7.5 :: GPU Core Clocks */ #define hsw__memory_writes__gpu_core_clocks__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen7.5 :: EU Active */ #define hsw__memory_writes__eu_active__read \ hsw__memory_reads__eu_active__read /* Memory Writes Distribution Gen7.5 :: TES EU Stall */ #define hsw__memory_writes__ds_eu_stall__read \ hsw__memory_reads__ds_eu_stall__read /* Memory Writes Distribution Gen7.5 :: Alpha Test Fails */ #define hsw__memory_writes__alpha_test_fails__read \ hsw__render_basic__alpha_test_fails__read /* Memory Writes Distribution Gen7.5 :: TES Threads Dispatched */ #define hsw__memory_writes__ds_threads__read \ hsw__render_basic__ds_threads__read /* Memory Writes Distribution Gen7.5 :: TES AVG Active per Thread */ #define hsw__memory_writes__ds_eu_active_per_thread__read \ hsw__render_basic__ds_eu_active_per_thread__read /* Memory Writes Distribution Gen7.5 :: GS Threads Dispatched */ #define hsw__memory_writes__gs_threads__read \ hsw__render_basic__gs_threads__read /* Memory Writes Distribution Gen7.5 :: GS EU Stall */ #define hsw__memory_writes__gs_eu_stall__read \ hsw__memory_reads__gs_eu_stall__read /* Memory Writes Distribution Gen7.5 :: VS Threads Dispatched */ #define hsw__memory_writes__vs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen7.5 :: FS Threads Dispatched */ #define hsw__memory_writes__ps_threads__read \ hsw__render_basic__ps_threads__read /* Memory Writes Distribution Gen7.5 :: GtiMscMemoryWrites */ #define hsw__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen7.5 :: CS Threads Dispatched */ #define hsw__memory_writes__cs_threads__read \ hsw__render_basic__cs_threads__read /* Memory Writes Distribution Gen7.5 :: CS AVG Active per Thread */ #define hsw__memory_writes__cs_eu_active_per_thread__read \ hsw__render_basic__cs_eu_active_per_thread__read /* Memory Writes Distribution Gen7.5 :: GtiCmdStreamerMemoryWrites */ #define hsw__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen7.5 :: GS AVG Stall per Thread */ #define hsw__memory_writes__gs_eu_stall_per_thread__read \ hsw__render_basic__gs_eu_stall_per_thread__read /* Memory Writes Distribution Gen7.5 :: GtiL3Writes */ #define hsw__memory_writes__gti_l3_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen7.5 :: GtiHizMemoryWrites */ #define hsw__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen7.5 :: GPU Time Elapsed */ #define hsw__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen7.5 :: AVG GPU Core Frequency */ #define hsw__memory_writes__avg_gpu_core_frequency__read \ hsw__memory_reads__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen7.5 :: AVG GPU Core Frequency */ #define hsw__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen7.5 :: FS AVG Stall per Thread */ #define hsw__memory_writes__ps_eu_stall_per_thread__read \ hsw__render_basic__ps_eu_stall_per_thread__read /* Memory Writes Distribution Gen7.5 :: GtiRccMemoryWrites */ #define hsw__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen7.5 :: TES EU Active */ #define hsw__memory_writes__ds_eu_active__read \ hsw__memory_reads__ds_eu_active__read /* Memory Writes Distribution Gen7.5 :: VS AVG Stall per Thread */ #define hsw__memory_writes__vs_eu_stall_per_thread__read \ hsw__render_basic__vs_eu_stall_per_thread__read /* Memory Writes Distribution Gen7.5 :: TCS EU Stall */ #define hsw__memory_writes__hs_eu_stall__read \ hsw__memory_reads__hs_eu_stall__read /* Memory Writes Distribution Gen7.5 :: GPU Busy */ #define hsw__memory_writes__gpu_busy__read \ hsw__memory_reads__gpu_busy__read /* Memory Writes Distribution Gen7.5 :: FS AVG Active per Thread */ #define hsw__memory_writes__ps_eu_active_per_thread__read \ hsw__render_basic__ps_eu_active_per_thread__read /* Memory Writes Distribution Gen7.5 :: Early Depth Test Fails */ #define hsw__memory_writes__early_depth_test_fails__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen7.5 :: LLC GPU Write Accesses */ static uint64_t hsw__memory_writes__llc_wr_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Memory Writes Distribution Gen7.5 :: GS EU Active */ #define hsw__memory_writes__gs_eu_active__read \ hsw__memory_reads__gs_eu_active__read /* Memory Writes Distribution Gen7.5 :: FS EU Active */ #define hsw__memory_writes__ps_eu_active__read \ hsw__memory_reads__ps_eu_active__read /* Memory Writes Distribution Gen7.5 :: GtiStcMemoryWrites */ #define hsw__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen7.5 :: TES AVG Stall per Thread */ #define hsw__memory_writes__ds_eu_stall_per_thread__read \ hsw__render_basic__ds_eu_stall_per_thread__read /* Memory Writes Distribution Gen7.5 :: GS AVG Active per Thread */ #define hsw__memory_writes__gs_eu_active_per_thread__read \ hsw__render_basic__gs_eu_active_per_thread__read /* Memory Writes Distribution Gen7.5 :: TCS Threads Dispatched */ #define hsw__memory_writes__hs_threads__read \ hsw__render_basic__hs_threads__read /* Memory Writes Distribution Gen7.5 :: TCS AVG Stall per Thread */ #define hsw__memory_writes__hs_eu_stall_per_thread__read \ hsw__render_basic__hs_eu_stall_per_thread__read /* Memory Writes Distribution Gen7.5 :: TCS EU Active */ #define hsw__memory_writes__hs_eu_active__read \ hsw__memory_reads__hs_eu_active__read /* Memory Writes Distribution Gen7.5 :: Samples Killed in FS */ #define hsw__memory_writes__samples_killed_in_ps__read \ hsw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen7.5 :: Late Depth Test Fails */ #define hsw__memory_writes__post_ps_depth_test_fails__read \ hsw__render_basic__post_ps_depth_test_fails__read /* Memory Writes Distribution Gen7.5 :: TCS AVG Active per Thread */ #define hsw__memory_writes__hs_eu_active_per_thread__read \ hsw__render_basic__hs_eu_active_per_thread__read /* Memory Writes Distribution Gen7.5 :: FS EU Stall */ #define hsw__memory_writes__ps_eu_stall__read \ hsw__memory_reads__ps_eu_stall__read /* Memory Writes Distribution Gen7.5 :: EU Stall */ #define hsw__memory_writes__eu_stall__read \ hsw__memory_reads__eu_stall__read /* Memory Writes Distribution Gen7.5 :: Early Hi-Depth Test Fails */ #define hsw__memory_writes__hi_depth_test_fails__read \ hsw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen7.5 :: VS EU Active */ #define hsw__memory_writes__vs_eu_active__read \ hsw__memory_reads__vs_eu_active__read /* Memory Writes Distribution Gen7.5 :: CS EU Active */ #define hsw__memory_writes__cs_eu_active__read \ hsw__memory_reads__cs_eu_active__read /* Memory Writes Distribution Gen7.5 :: CS AVG Stall per Thread */ #define hsw__memory_writes__cs_eu_stall_per_thread__read \ hsw__render_basic__cs_eu_stall_per_thread__read /* Memory Writes Distribution Gen7.5 :: Late Stencil Test Fails */ #define hsw__memory_writes__post_ps_stencil_test_fails__read \ hsw__render_basic__post_ps_stencil_test_fails__read /* Memory Writes Distribution Gen7.5 :: GtiSoMemoryWrites */ #define hsw__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen7.5 :: VS AVG Active per Thread */ #define hsw__memory_writes__vs_eu_active_per_thread__read \ hsw__render_basic__vs_eu_active_per_thread__read /* Memory Writes Distribution Gen7.5 :: GtiRczMemoryWrites */ #define hsw__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen7.5 :: CS EU Stall */ #define hsw__memory_writes__cs_eu_stall__read \ hsw__memory_reads__cs_eu_stall__read /* Memory Writes Distribution Gen7.5 :: Samples Written */ #define hsw__memory_writes__samples_written__read \ hsw__render_basic__samples_written__read /* Memory Writes Distribution Gen7.5 :: GtiMemoryWrites */ #define hsw__memory_writes__gti_memory_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen7.5 :: VS EU Stall */ #define hsw__memory_writes__vs_eu_stall__read \ hsw__memory_reads__vs_eu_stall__read /* Metric set SamplerBalance :: GPU Core Clocks */ #define hsw__sampler_balance__gpu_core_clocks__read \ hsw__compute_extended__gpu_clocks__read /* Metric set SamplerBalance :: EU Active */ static float hsw__sampler_balance__eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 0]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: TES EU Stall */ static float hsw__sampler_balance__ds_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: Sampler L2 cache misses (ss3) */ static uint64_t hsw__sampler_balance__sampler3_l2_cache_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ C 0 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = accumulator[query->c_offset + 0]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Metric set SamplerBalance :: Alpha Test Fails */ #define hsw__sampler_balance__alpha_test_fails__read \ hsw__render_basic__alpha_test_fails__read /* Metric set SamplerBalance :: TES Threads Dispatched */ #define hsw__sampler_balance__ds_threads__read \ hsw__render_basic__ds_threads__read /* Metric set SamplerBalance :: TES AVG Active per Thread */ #define hsw__sampler_balance__ds_eu_active_per_thread__read \ hsw__render_basic__ds_eu_active_per_thread__read /* Metric set SamplerBalance :: GS Threads Dispatched */ #define hsw__sampler_balance__gs_threads__read \ hsw__render_basic__gs_threads__read /* Metric set SamplerBalance :: GS EU Stall */ static float hsw__sampler_balance__gs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 23]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: CS EU Active */ static float hsw__sampler_balance__cs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: VS EU Active */ static float hsw__sampler_balance__vs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 2]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: TCS EU Active */ static float hsw__sampler_balance__hs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: TES EU Active */ static float hsw__sampler_balance__ds_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: GS EU Active */ static float hsw__sampler_balance__gs_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: FS EU Active */ static float hsw__sampler_balance__ps_eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: CS EU Stall */ static float hsw__sampler_balance__cs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 18]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: EU Stall */ static float hsw__sampler_balance__eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 1]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: VS EU Stall */ static float hsw__sampler_balance__vs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 3]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: TCS EU Stall */ static float hsw__sampler_balance__hs_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: FS EU Stall */ static float hsw__sampler_balance__ps_eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 28]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Metric set SamplerBalance :: GPU Time Elapsed */ #define hsw__sampler_balance__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set SamplerBalance :: CS Duration */ static uint64_t hsw__sampler_balance__cs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 18 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 18]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Metric set SamplerBalance :: VS Threads Dispatched */ #define hsw__sampler_balance__vs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set SamplerBalance :: FS Threads Dispatched */ #define hsw__sampler_balance__ps_threads__read \ hsw__render_basic__ps_threads__read /* Metric set SamplerBalance :: TES Duration */ static uint64_t hsw__sampler_balance__ds_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 13 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 13]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Metric set SamplerBalance :: GS Duration */ static uint64_t hsw__sampler_balance__gs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 23 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 23]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Metric set SamplerBalance :: CS Threads Dispatched */ #define hsw__sampler_balance__cs_threads__read \ hsw__render_basic__cs_threads__read /* Metric set SamplerBalance :: CS AVG Active per Thread */ #define hsw__sampler_balance__cs_eu_active_per_thread__read \ hsw__render_basic__cs_eu_active_per_thread__read /* Metric set SamplerBalance :: Sampler L2 cache misses */ static uint64_t hsw__sampler_balance__sampler_l2_cache_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD C 3 READ UADD C 2 READ UADD C 1 READ UADD C 0 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = accumulator[query->c_offset + 6]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->c_offset + 5]; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = accumulator[query->c_offset + 4]; uint64_t tmp6 = tmp4 + tmp5; uint64_t tmp7 = accumulator[query->c_offset + 3]; uint64_t tmp8 = tmp6 + tmp7; uint64_t tmp9 = accumulator[query->c_offset + 2]; uint64_t tmp10 = tmp8 + tmp9; uint64_t tmp11 = accumulator[query->c_offset + 1]; uint64_t tmp12 = tmp10 + tmp11; uint64_t tmp13 = accumulator[query->c_offset + 0]; uint64_t tmp14 = tmp12 + tmp13; return tmp14; } /* Metric set SamplerBalance :: GS AVG Stall per Thread */ #define hsw__sampler_balance__gs_eu_stall_per_thread__read \ hsw__render_basic__gs_eu_stall_per_thread__read /* Metric set SamplerBalance :: Sampler L2 cache misses (ss2) */ static uint64_t hsw__sampler_balance__sampler2_l2_cache_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ C 2 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = accumulator[query->c_offset + 2]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Metric set SamplerBalance :: AVG GPU Core Frequency */ static uint64_t hsw__sampler_balance__avg_gpu_core_frequency__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ uint64_t tmp0 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * 1000000000; uint64_t tmp1 = tmp0; uint64_t tmp2 = hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Metric set SamplerBalance :: AVG GPU Core Frequency */ #define hsw__sampler_balance__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set SamplerBalance :: EU Idle */ static float hsw__sampler_balance__eu_idle__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 100 $EuActive $EuStall FADD FSUB */ double tmp0 = hsw__sampler_balance__eu_active__read(perf, query, accumulator) + hsw__sampler_balance__eu_stall__read(perf, query, accumulator); double tmp1 = 100 - tmp0; return tmp1; } /* Metric set SamplerBalance :: FS AVG Stall per Thread */ #define hsw__sampler_balance__ps_eu_stall_per_thread__read \ hsw__render_basic__ps_eu_stall_per_thread__read /* Metric set SamplerBalance :: VS AVG Stall per Thread */ #define hsw__sampler_balance__vs_eu_stall_per_thread__read \ hsw__render_basic__vs_eu_stall_per_thread__read /* Metric set SamplerBalance :: GPU Busy */ static float hsw__sampler_balance__gpu_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 41]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Metric set SamplerBalance :: FS AVG Active per Thread */ #define hsw__sampler_balance__ps_eu_active_per_thread__read \ hsw__render_basic__ps_eu_active_per_thread__read /* Metric set SamplerBalance :: Early Depth Test Fails */ #define hsw__sampler_balance__early_depth_test_fails__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set SamplerBalance :: TCS Duration */ static uint64_t hsw__sampler_balance__hs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 8 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 8]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Metric set SamplerBalance :: TES AVG Stall per Thread */ #define hsw__sampler_balance__ds_eu_stall_per_thread__read \ hsw__render_basic__ds_eu_stall_per_thread__read /* Metric set SamplerBalance :: GS AVG Active per Thread */ #define hsw__sampler_balance__gs_eu_active_per_thread__read \ hsw__render_basic__gs_eu_active_per_thread__read /* Metric set SamplerBalance :: TCS Threads Dispatched */ #define hsw__sampler_balance__hs_threads__read \ hsw__render_basic__hs_threads__read /* Metric set SamplerBalance :: TCS AVG Stall per Thread */ #define hsw__sampler_balance__hs_eu_stall_per_thread__read \ hsw__render_basic__hs_eu_stall_per_thread__read /* Metric set SamplerBalance :: Samples Killed in FS */ #define hsw__sampler_balance__samples_killed_in_ps__read \ hsw__render_basic__samples_killed_in_ps__read /* Metric set SamplerBalance :: Late Depth Test Fails */ #define hsw__sampler_balance__post_ps_depth_test_fails__read \ hsw__render_basic__post_ps_depth_test_fails__read /* Metric set SamplerBalance :: TCS AVG Active per Thread */ #define hsw__sampler_balance__hs_eu_active_per_thread__read \ hsw__render_basic__hs_eu_active_per_thread__read /* Metric set SamplerBalance :: FS Duration */ static uint64_t hsw__sampler_balance__ps_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 28 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 28]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Metric set SamplerBalance :: Sampler L2 cache misses (ss1) */ static uint64_t hsw__sampler_balance__sampler1_l2_cache_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ C 4 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = accumulator[query->c_offset + 4]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Metric set SamplerBalance :: Early Hi-Depth Test Fails */ #define hsw__sampler_balance__hi_depth_test_fails__read \ hsw__render_basic__hi_depth_test_fails__read /* Metric set SamplerBalance :: CS AVG Stall per Thread */ #define hsw__sampler_balance__cs_eu_stall_per_thread__read \ hsw__render_basic__cs_eu_stall_per_thread__read /* Metric set SamplerBalance :: Late Stencil Test Fails */ #define hsw__sampler_balance__post_ps_stencil_test_fails__read \ hsw__render_basic__post_ps_stencil_test_fails__read /* Metric set SamplerBalance :: Sampler L2 cache misses (ss0) */ static uint64_t hsw__sampler_balance__sampler0_l2_cache_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ C 6 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = accumulator[query->c_offset + 6]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Metric set SamplerBalance :: VS AVG Active per Thread */ #define hsw__sampler_balance__vs_eu_active_per_thread__read \ hsw__render_basic__vs_eu_active_per_thread__read /* Metric set SamplerBalance :: VS Duration */ static uint64_t hsw__sampler_balance__vs_duration__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 3 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 2]; uint64_t tmp1 = accumulator[query->a_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = accumulator[query->a_offset + 2]; uint64_t tmp4 = accumulator[query->a_offset + 7]; uint64_t tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->a_offset + 12]; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->a_offset + 17]; uint64_t tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->a_offset + 22]; uint64_t tmp11 = tmp9 + tmp10; uint64_t tmp12 = accumulator[query->a_offset + 27]; uint64_t tmp13 = tmp11 + tmp12; uint64_t tmp14 = tmp2; uint64_t tmp15 = tmp13; uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; uint64_t tmp17 = accumulator[query->a_offset + 3]; uint64_t tmp18 = accumulator[query->a_offset + 1]; uint64_t tmp19 = tmp17 * tmp18; uint64_t tmp20 = accumulator[query->a_offset + 3]; uint64_t tmp21 = accumulator[query->a_offset + 8]; uint64_t tmp22 = tmp20 + tmp21; uint64_t tmp23 = accumulator[query->a_offset + 13]; uint64_t tmp24 = tmp22 + tmp23; uint64_t tmp25 = accumulator[query->a_offset + 18]; uint64_t tmp26 = tmp24 + tmp25; uint64_t tmp27 = accumulator[query->a_offset + 23]; uint64_t tmp28 = tmp26 + tmp27; uint64_t tmp29 = accumulator[query->a_offset + 28]; uint64_t tmp30 = tmp28 + tmp29; uint64_t tmp31 = tmp19; uint64_t tmp32 = tmp30; uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; uint64_t tmp34 = tmp16 + tmp33; uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(perf, query, accumulator); uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(perf, query, accumulator) * perf->sys_vars.n_eus; uint64_t tmp37 = tmp36 * 1000; uint64_t tmp38 = tmp35; uint64_t tmp39 = tmp37; uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; return tmp40; } /* Metric set SamplerBalance :: Samples Written */ #define hsw__sampler_balance__samples_written__read \ hsw__render_basic__samples_written__read /* Render Metrics Basic Gen8 :: GPU Core Clocks */ static uint64_t bdw__render_basic__gpu_core_clocks__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; return tmp0; } /* Render Metrics Basic Gen8 :: EU Active */ static float bdw__render_basic__eu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 7]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: L3 Misses */ #define bdw__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen8 :: GTI L3 Throughput */ #define bdw__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen8 :: EU Both FPU Pipes Active */ static float bdw__render_basic__eu_fpu_both_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 9]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: Sampler Cache Misses */ static uint64_t bdw__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ UADD 8 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 8; return tmp3; } /* Render Metrics Basic Gen8 :: VS Send Pipe Active */ static float bdw__render_basic__vs_send_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 12]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: Sampler 1 Bottleneck */ static float bdw__render_basic__sampler1_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen8 :: VS FPU1 Pipe Active */ static float bdw__render_basic__vs_fpu1_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 11]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: GS Threads Dispatched */ #define bdw__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen8 :: L3 Sampler Throughput */ static uint64_t bdw__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses 64 UMUL */ uint64_t tmp0 = bdw__render_basic__sampler_l1_misses__read(perf, query, accumulator) * 64; return tmp0; } /* Render Metrics Basic Gen8 :: Early Hi-Depth Test Fails */ static uint64_t bdw__render_basic__hi_depth_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 22 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 22]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: FS Both FPU Active */ static float bdw__render_basic__ps_eu_both_fpu_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 18]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: VS Threads Dispatched */ static uint64_t bdw__render_basic__vs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 1 READ */ uint64_t tmp0 = accumulator[query->a_offset + 1]; return tmp0; } /* Render Metrics Basic Gen8 :: FS Threads Dispatched */ static uint64_t bdw__render_basic__ps_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 6 READ */ uint64_t tmp0 = accumulator[query->a_offset + 6]; return tmp0; } /* Render Metrics Basic Gen8 :: Sampler 0 Busy */ static float bdw__render_basic__sampler0_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen8 :: Sampler 1 Busy */ static float bdw__render_basic__sampler1_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 1 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen8 :: Samplers Busy */ static float bdw__render_basic__samplers_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $Sampler0Busy $Sampler1Busy FMAX */ double tmp0 = bdw__render_basic__sampler0_busy__read(perf, query, accumulator); double tmp1 = bdw__render_basic__sampler1_busy__read(perf, query, accumulator); double tmp2 = MAX(tmp0, tmp1); return tmp2; } /* Render Metrics Basic Gen8 :: GTI Fixed Pipe Throughput */ static uint64_t bdw__render_basic__gti_vf_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ B 7 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = accumulator[query->b_offset + 7]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Render Metrics Basic Gen8 :: Shader Barrier Messages */ #define bdw__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen8 :: Sampler 0 Bottleneck */ static float bdw__render_basic__sampler0_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen8 :: Sampler Texels */ static uint64_t bdw__render_basic__sampler_texels__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 28 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 28]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: Pixels Failing Tests */ static uint64_t bdw__render_basic__pixels_failing_post_ps_tests__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 25 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 25]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: GPU Time Elapsed */ #define bdw__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen8 :: AVG GPU Core Frequency */ static uint64_t bdw__render_basic__avg_gpu_core_frequency__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator) * 1000000000; uint64_t tmp1 = tmp0; uint64_t tmp2 = bdw__render_basic__gpu_time__read(perf, query, accumulator); uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Render Metrics Basic Gen8 :: AVG GPU Core Frequency */ #define bdw__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen8 :: Sampler Texels Misses */ static uint64_t bdw__render_basic__sampler_texel_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 29 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 29]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: CS Threads Dispatched */ static uint64_t bdw__render_basic__cs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 4 READ */ uint64_t tmp0 = accumulator[query->a_offset + 4]; return tmp0; } /* Render Metrics Basic Gen8 :: Shader Memory Accesses */ static uint64_t bdw__render_basic__shader_memory_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 32 READ */ uint64_t tmp0 = accumulator[query->a_offset + 32]; return tmp0; } /* Render Metrics Basic Gen8 :: L3 Lookup Accesses w/o IC */ static uint64_t bdw__render_basic__l3_lookups__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ uint64_t tmp0 = bdw__render_basic__sampler_l1_misses__read(perf, query, accumulator) + bdw__render_basic__shader_memory_accesses__read(perf, query, accumulator); return tmp0; } /* Render Metrics Basic Gen8 :: SLM Bytes Read */ static uint64_t bdw__render_basic__slm_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 30 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 30]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen8 :: GTI Read Throughput */ static uint64_t bdw__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen8 :: PS FPU1 Pipe Active */ static float bdw__render_basic__ps_fpu1_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 16 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 16]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: PS Send Pipeline Active */ static float bdw__render_basic__ps_send_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 17]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: Rasterized Pixels */ static uint64_t bdw__render_basic__rasterized_pixels__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 21 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 21]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: GPU Busy */ static float bdw__render_basic__gpu_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 0 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 0]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics Basic Gen8 :: GTI Depth Throughput */ static uint64_t bdw__render_basic__gti_depth_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ C 1 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Render Metrics Basic Gen8 :: VS FPU0 Pipe Active */ static float bdw__render_basic__vs_fpu0_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 10 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 10]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: PS FPU0 Pipe Active */ static float bdw__render_basic__ps_fpu0_active__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 15 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 15]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: DS Threads Dispatched */ static uint64_t bdw__render_basic__ds_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 3 READ */ uint64_t tmp0 = accumulator[query->a_offset + 3]; return tmp0; } /* Render Metrics Basic Gen8 :: Samples Written */ static uint64_t bdw__render_basic__samples_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 26 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 26]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: EU Stall */ static float bdw__render_basic__eu_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Render Metrics Basic Gen8 :: Samples Blended */ static uint64_t bdw__render_basic__samples_blended__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 27 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 27]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: Early Depth Test Fails */ static uint64_t bdw__render_basic__early_depth_test_fails__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 23 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 23]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: Samplers Bottleneck */ static float bdw__render_basic__sampler_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $Sampler0Bottleneck $Sampler1Bottleneck FMAX */ double tmp0 = bdw__render_basic__sampler0_bottleneck__read(perf, query, accumulator); double tmp1 = bdw__render_basic__sampler1_bottleneck__read(perf, query, accumulator); double tmp2 = MAX(tmp0, tmp1); return tmp2; } /* Render Metrics Basic Gen8 :: GTI HDC TLB Lookup Throughput */ static uint64_t bdw__render_basic__gti_hdc_lookups_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen8 :: GTI RCC Throughput */ static uint64_t bdw__render_basic__gti_rcc_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ C 3 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = accumulator[query->c_offset + 3]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Render Metrics Basic Gen8 :: HS Threads Dispatched */ static uint64_t bdw__render_basic__hs_threads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 2 READ */ uint64_t tmp0 = accumulator[query->a_offset + 2]; return tmp0; } /* Render Metrics Basic Gen8 :: GTI Write Throughput */ #define bdw__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen8 :: SLM Bytes Written */ static uint64_t bdw__render_basic__slm_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 31 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 31]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen8 :: L3 Shader Throughput */ static uint64_t bdw__render_basic__l3_shader_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 30 READ A 31 READ $ShaderMemoryAccesses UADD UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 30]; uint64_t tmp1 = accumulator[query->a_offset + 31]; uint64_t tmp2 = tmp1 + bdw__render_basic__shader_memory_accesses__read(perf, query, accumulator); uint64_t tmp3 = tmp0 + tmp2; uint64_t tmp4 = tmp3 * 64; return tmp4; } /* Render Metrics Basic Gen8 :: Samples Killed in FS */ static uint64_t bdw__render_basic__samples_killed_in_ps__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 24 READ 4 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 24]; uint64_t tmp1 = tmp0 * 4; return tmp1; } /* Render Metrics Basic Gen8 :: Shader Atomic Memory Accesses */ static uint64_t bdw__render_basic__shader_atomics__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 34 READ */ uint64_t tmp0 = accumulator[query->a_offset + 34]; return tmp0; } /* Compute Metrics Basic Gen8 :: GPU Core Clocks */ #define bdw__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen8 :: EU Active */ #define bdw__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen8 :: Untyped Bytes Read */ static uint64_t bdw__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ B 7 READ C 0 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = accumulator[query->b_offset + 7]; uint64_t tmp2 = accumulator[query->c_offset + 0]; uint64_t tmp3 = tmp1 + tmp2; uint64_t tmp4 = tmp0 + tmp3; uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp6 = tmp4 * tmp5; return tmp6; } /* Compute Metrics Basic Gen8 :: EU Both FPU Pipes Active */ #define bdw__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen8 :: Typed Bytes Written */ static uint64_t bdw__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ B 4 READ B 5 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = accumulator[query->b_offset + 4]; uint64_t tmp2 = accumulator[query->b_offset + 5]; uint64_t tmp3 = tmp1 + tmp2; uint64_t tmp4 = tmp0 + tmp3; uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp6 = tmp4 * tmp5; return tmp6; } /* Compute Metrics Basic Gen8 :: EU FPU0 Pipe Active */ #define bdw__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen8 :: EU FPU1 Pipe Active */ #define bdw__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen8 :: EU AVG IPC Rate */ static float bdw__compute_basic__eu_avg_ipc_rate__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 9 READ A 10 READ A 11 READ UADD A 9 READ USUB FDIV 1 FADD */ uint64_t tmp0 = accumulator[query->a_offset + 9]; uint64_t tmp1 = accumulator[query->a_offset + 10]; uint64_t tmp2 = accumulator[query->a_offset + 11]; uint64_t tmp3 = tmp1 + tmp2; uint64_t tmp4 = accumulator[query->a_offset + 9]; uint64_t tmp5 = tmp3 - tmp4; double tmp6 = tmp0; double tmp7 = tmp5; double tmp8 = tmp7 ? tmp6 / tmp7 : 0; double tmp9 = tmp8 + 1; return tmp9; } /* Compute Metrics Basic Gen8 :: GS Threads Dispatched */ #define bdw__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen8 :: Early Hi-Depth Test Fails */ #define bdw__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen8 :: VS Threads Dispatched */ #define bdw__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen8 :: FS Threads Dispatched */ #define bdw__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen8 :: Shader Barrier Messages */ #define bdw__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen8 :: Sampler Texels */ #define bdw__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen8 :: Pixels Failing Tests */ #define bdw__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen8 :: GPU Time Elapsed */ #define bdw__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen8 :: Sampler Texels Misses */ #define bdw__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen8 :: CS Threads Dispatched */ #define bdw__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen8 :: SLM Bytes Read */ #define bdw__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen8 :: GTI Read Throughput */ #define bdw__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen8 :: Untyped Writes */ static uint64_t bdw__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ C 2 READ C 3 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = accumulator[query->c_offset + 2]; uint64_t tmp2 = accumulator[query->c_offset + 3]; uint64_t tmp3 = tmp1 + tmp2; uint64_t tmp4 = tmp0 + tmp3; uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp6 = tmp4 * tmp5; return tmp6; } /* Compute Metrics Basic Gen8 :: GPU Busy */ #define bdw__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen8 :: Rasterized Pixels */ #define bdw__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen8 :: Typed Bytes Read */ static uint64_t bdw__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ B 2 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = accumulator[query->b_offset + 2]; uint64_t tmp3 = tmp1 + tmp2; uint64_t tmp4 = tmp0 + tmp3; uint64_t tmp5 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp6 = tmp4 * tmp5; return tmp6; } /* Compute Metrics Basic Gen8 :: DS Threads Dispatched */ #define bdw__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen8 :: EU Thread Occupancy */ static float bdw__compute_basic__eu_thread_occupancy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ 8 UMUL $EuCoresTotalCount UDIV $EuThreadsCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = tmp0 * 8; uint64_t tmp2 = tmp1; uint64_t tmp3 = perf->sys_vars.n_eus; uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; uint64_t tmp5 = tmp4; uint64_t tmp6 = perf->sys_vars.eu_threads_count; uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0; uint64_t tmp8 = tmp7 * 100; double tmp9 = tmp8; double tmp10 = bdw__compute_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp11 = tmp10 ? tmp9 / tmp10 : 0; return tmp11; } /* Compute Metrics Basic Gen8 :: EU Stall */ #define bdw__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen8 :: Samples Blended */ #define bdw__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen8 :: Early Depth Test Fails */ #define bdw__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen8 :: Shader Memory Accesses */ #define bdw__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen8 :: HS Threads Dispatched */ #define bdw__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen8 :: GTI Write Throughput */ #define bdw__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen8 :: SLM Bytes Written */ #define bdw__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen8 :: L3 Shader Throughput */ #define bdw__compute_basic__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Compute Metrics Basic Gen8 :: Samples Killed in FS */ #define bdw__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen8 :: Samples Written */ #define bdw__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen8 :: Shader Atomic Memory Accesses */ #define bdw__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen8 :: EU Send Pipe Active */ #define bdw__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */ #define bdw__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile :: EU Active */ #define bdw__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */ #define bdw__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */ static float bdw__render_pipe_profile__hi_depth_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */ #define bdw__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */ #define bdw__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */ #define bdw__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */ #define bdw__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */ #define bdw__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */ static float bdw__render_pipe_profile__bc_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: HS Stall */ static float bdw__render_pipe_profile__hs_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */ #define bdw__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile :: Sampler Texels */ #define bdw__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */ #define bdw__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */ #define bdw__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ #define bdw__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ #define bdw__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */ #define bdw__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */ #define bdw__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */ static float bdw__render_pipe_profile__vf_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */ #define bdw__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */ static float bdw__render_pipe_profile__sf_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: Sampler Accesses */ static uint64_t bdw__render_pipe_profile__sampler_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 28 READ */ uint64_t tmp0 = accumulator[query->a_offset + 28]; return tmp0; } /* Render Metrics for 3D Pipeline Profile :: SF Stall */ static float bdw__render_pipe_profile__sf_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: GPU Busy */ #define bdw__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */ #define bdw__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile :: CL Stall */ static float bdw__render_pipe_profile__cl_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */ static float bdw__render_pipe_profile__so_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */ #define bdw__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */ #define bdw__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile :: Samples Written */ #define bdw__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */ #define bdw__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: EU Stall */ #define bdw__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */ static float bdw__render_pipe_profile__cl_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: DS Stall */ static float bdw__render_pipe_profile__ds_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: Early Depth Bottleneck */ static float bdw__render_pipe_profile__early_depth_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: Samples Blended */ #define bdw__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */ #define bdw__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */ #define bdw__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */ #define bdw__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */ #define bdw__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */ #define bdw__render_pipe_profile__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */ #define bdw__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile :: SO Stall */ static float bdw__render_pipe_profile__so_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = tmp0 * 100; double tmp2 = tmp1; double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(perf, query, accumulator); double tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */ #define bdw__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen8 :: GPU Core Clocks */ #define bdw__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen8 :: EU Active */ #define bdw__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen8 :: GtiL3Bank0Reads */ #define bdw__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen8 :: GS Threads Dispatched */ #define bdw__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen8 :: GtiRingAccesses */ static uint64_t bdw__memory_reads__gti_ring_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Memory Reads Distribution Gen8 :: Early Hi-Depth Test Fails */ #define bdw__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen8 :: VS Threads Dispatched */ #define bdw__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen8 :: FS Threads Dispatched */ #define bdw__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen8 :: GtiL3Bank3Reads */ #define bdw__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen8 :: Shader Barrier Messages */ #define bdw__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen8 :: GtiRsMemoryReads */ #define bdw__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen8 :: Sampler Texels */ #define bdw__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen8 :: Pixels Failing Tests */ #define bdw__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen8 :: GtiHizMemoryReads */ #define bdw__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen8 :: GPU Time Elapsed */ #define bdw__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen8 :: AVG GPU Core Frequency */ #define bdw__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen8 :: AVG GPU Core Frequency */ #define bdw__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen8 :: Sampler Texels Misses */ #define bdw__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen8 :: GtiRccMemoryReads */ #define bdw__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen8 :: CS Threads Dispatched */ #define bdw__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen8 :: SLM Bytes Read */ #define bdw__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen8 :: GtiL3Bank1Reads */ #define bdw__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen8 :: GPU Busy */ #define bdw__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen8 :: GtiCmdStreamerMemoryReads */ #define bdw__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen8 :: GtiL3Bank2Reads */ #define bdw__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen8 :: GtiMemoryReads */ #define bdw__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen8 :: Rasterized Pixels */ #define bdw__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen8 :: GtiRczMemoryReads */ #define bdw__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen8 :: DS Threads Dispatched */ #define bdw__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen8 :: Samples Written */ #define bdw__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen8 :: EU Stall */ #define bdw__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen8 :: Samples Blended */ #define bdw__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen8 :: Early Depth Test Fails */ #define bdw__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen8 :: GtiMscMemoryReads */ #define bdw__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen8 :: GtiVfMemoryReads */ #define bdw__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen8 :: GtiStcMemoryReads */ #define bdw__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen8 :: Shader Memory Accesses */ #define bdw__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen8 :: HS Threads Dispatched */ #define bdw__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen8 :: SLM Bytes Written */ #define bdw__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen8 :: L3 Shader Throughput */ #define bdw__memory_reads__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Memory Reads Distribution Gen8 :: Samples Killed in FS */ #define bdw__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen8 :: GtiL3Reads */ static uint64_t bdw__memory_reads__gti_l3_reads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $GtiL3Bank0Reads $GtiL3Bank1Reads $GtiL3Bank2Reads $GtiL3Bank3Reads UADD UADD UADD */ uint64_t tmp0 = bdw__memory_reads__gti_l3_bank2_reads__read(perf, query, accumulator) + bdw__memory_reads__gti_l3_bank3_reads__read(perf, query, accumulator); uint64_t tmp1 = bdw__memory_reads__gti_l3_bank1_reads__read(perf, query, accumulator) + tmp0; uint64_t tmp2 = bdw__memory_reads__gti_l3_bank0_reads__read(perf, query, accumulator) + tmp1; return tmp2; } /* Memory Reads Distribution Gen8 :: Shader Atomic Memory Accesses */ #define bdw__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen8 :: GPU Core Clocks */ #define bdw__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen8 :: EU Active */ #define bdw__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen8 :: GtiMemoryWrites */ #define bdw__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen8 :: GS Threads Dispatched */ #define bdw__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen8 :: GtiRingAccesses */ #define bdw__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen8 :: Early Hi-Depth Test Fails */ #define bdw__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen8 :: VS Threads Dispatched */ #define bdw__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen8 :: FS Threads Dispatched */ #define bdw__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen8 :: GtiMscMemoryWrites */ #define bdw__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen8 :: Shader Barrier Messages */ #define bdw__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen8 :: GtiCmdStreamerMemoryWrites */ #define bdw__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen8 :: Sampler Texels */ #define bdw__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen8 :: Pixels Failing Tests */ #define bdw__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen8 :: GtiL3Bank0Writes */ #define bdw__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen8 :: GtiL3Bank1Writes */ #define bdw__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen8 :: GtiL3Bank2Writes */ #define bdw__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen8 :: GtiL3Bank3Writes */ #define bdw__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen8 :: GtiL3Writes */ #define bdw__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen8 :: GPU Time Elapsed */ #define bdw__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen8 :: AVG GPU Core Frequency */ #define bdw__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen8 :: AVG GPU Core Frequency */ #define bdw__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen8 :: Sampler Texels Misses */ #define bdw__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen8 :: CS Threads Dispatched */ #define bdw__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen8 :: SLM Bytes Read */ #define bdw__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen8 :: GtiRccMemoryWrites */ #define bdw__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen8 :: GtiSoMemoryWrites */ #define bdw__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen8 :: GPU Busy */ #define bdw__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen8 :: GtiStcMemoryWrites */ #define bdw__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen8 :: Rasterized Pixels */ #define bdw__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen8 :: DS Threads Dispatched */ #define bdw__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen8 :: Samples Written */ #define bdw__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen8 :: EU Stall */ #define bdw__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen8 :: Samples Blended */ #define bdw__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen8 :: Early Depth Test Fails */ #define bdw__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen8 :: Shader Memory Accesses */ #define bdw__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen8 :: HS Threads Dispatched */ #define bdw__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen8 :: GtiRczMemoryWrites */ #define bdw__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen8 :: SLM Bytes Written */ #define bdw__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen8 :: L3 Shader Throughput */ #define bdw__memory_writes__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Memory Writes Distribution Gen8 :: Samples Killed in FS */ #define bdw__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen8 :: GtiHizMemoryWrites */ #define bdw__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen8 :: Shader Atomic Memory Accesses */ #define bdw__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen8 :: GPU Core Clocks */ #define bdw__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen8 :: EU Active */ #define bdw__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen8 :: EU Both FPU Pipes Active */ #define bdw__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen8 :: EU FPU0 Pipe Active */ #define bdw__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen8 :: EU FPU1 Pipe Active */ #define bdw__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen8 :: EU AVG IPC Rate */ #define bdw__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen8 :: Typed Writes 0 */ #define bdw__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen8 :: EuTypedAtomics0 */ #define bdw__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen8 :: Typed Atomics 0 */ #define bdw__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen8 :: TypedAtomicsPerCacheLine */ #define bdw__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen8 :: EuUntypedReads0 */ #define bdw__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen8 :: Untyped Writes 0 */ #define bdw__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen8 :: EuUntypedAtomics0 */ #define bdw__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen8 :: EuUntypedWrites0 */ #define bdw__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen8 :: EuA64UntypedWrites0 */ #define bdw__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen8 :: UntypedWritesPerCacheLine */ static float bdw__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuUntypedWrites0 $EuA64UntypedWrites0 UADD $UntypedWrites0 FDIV */ uint64_t tmp0 = bdw__compute_extended__eu_untyped_writes0__read(perf, query, accumulator) + bdw__compute_extended__eu_a64_untyped_writes0__read(perf, query, accumulator); double tmp1 = tmp0; double tmp2 = bdw__compute_extended__untyped_writes0__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Compute Metrics Extended Gen8 :: Shader Barrier Messages */ #define bdw__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen8 :: Sampler Texels */ #define bdw__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen8 :: GPU Time Elapsed */ #define bdw__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen8 :: Sampler Texels Misses */ #define bdw__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen8 :: CS Threads Dispatched */ #define bdw__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen8 :: SLM Bytes Read */ #define bdw__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen8 :: EuTypedWrites0 */ #define bdw__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen8 :: TypedWritesPerCacheLine */ #define bdw__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen8 :: Typed Reads 0 */ #define bdw__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen8 :: Untyped Reads 0 */ #define bdw__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen8 :: EuA64UntypedReads0 */ #define bdw__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen8 :: EU Thread Occupancy */ #define bdw__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen8 :: EU Stall */ #define bdw__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen8 :: EuTypedReads0 */ #define bdw__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen8 :: UntypedReadsPerCacheLine */ static float bdw__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuUntypedReads0 $EuA64UntypedReads0 UADD $UntypedReads0 FDIV */ uint64_t tmp0 = bdw__compute_extended__eu_untyped_reads0__read(perf, query, accumulator) + bdw__compute_extended__eu_a64_untyped_reads0__read(perf, query, accumulator); double tmp1 = tmp0; double tmp2 = bdw__compute_extended__untyped_reads0__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Compute Metrics Extended Gen8 :: Shader Memory Accesses */ #define bdw__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen8 :: TypedReadsPerCacheLine */ #define bdw__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen8 :: SLM Bytes Written */ #define bdw__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen8 :: L3 Shader Throughput */ #define bdw__compute_extended__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Compute Metrics Extended Gen8 :: Shader Atomic Memory Accesses */ #define bdw__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen8 :: EU Send Pipe Active */ #define bdw__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen8 :: GPU Core Clocks */ #define bdw__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen8 :: EU Active */ #define bdw__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 03 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank03_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: L3 Accesses */ static uint64_t bdw__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ C 1 READ B 2 READ B 3 READ C 2 READ C 3 READ B 6 READ B 7 READ UADD UADD UADD UADD UADD UADD UADD 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; uint64_t tmp2 = accumulator[query->b_offset + 2]; uint64_t tmp3 = accumulator[query->b_offset + 3]; uint64_t tmp4 = accumulator[query->c_offset + 2]; uint64_t tmp5 = accumulator[query->c_offset + 3]; uint64_t tmp6 = accumulator[query->b_offset + 6]; uint64_t tmp7 = accumulator[query->b_offset + 7]; uint64_t tmp8 = tmp6 + tmp7; uint64_t tmp9 = tmp5 + tmp8; uint64_t tmp10 = tmp4 + tmp9; uint64_t tmp11 = tmp3 + tmp10; uint64_t tmp12 = tmp2 + tmp11; uint64_t tmp13 = tmp1 + tmp12; uint64_t tmp14 = tmp0 + tmp13; uint64_t tmp15 = tmp14 * 2; return tmp15; } /* Compute Metrics L3 Cache Gen8 :: EU Both FPU Pipes Active */ #define bdw__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen8 :: L3 Total Throughput */ static uint64_t bdw__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Accesses 64 UMUL */ uint64_t tmp0 = bdw__compute_l3_cache__l3_accesses__read(perf, query, accumulator) * 64; return tmp0; } /* Compute Metrics L3 Cache Gen8 :: EU FPU0 Pipe Active */ #define bdw__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen8 :: EU FPU1 Pipe Active */ #define bdw__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen8 :: EU AVG IPC Rate */ #define bdw__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen8 :: EU FPU0 Binary Instruction */ #define bdw__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen8 :: GS Threads Dispatched */ #define bdw__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen8 :: Early Hi-Depth Test Fails */ #define bdw__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen8 :: VS Threads Dispatched */ #define bdw__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen8 :: FS Threads Dispatched */ #define bdw__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen8 :: EU FPU0 Hybrid Instruction */ static float bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Compute Metrics L3 Cache Gen8 :: L3 Misses */ static uint64_t bdw__compute_l3_cache__l3_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ C 5 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = accumulator[query->c_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Compute Metrics L3 Cache Gen8 :: Shader Barrier Messages */ #define bdw__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 00 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank00_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: EU FPU0 Move Instruction */ static float bdw__compute_l3_cache__eu_move_fpu0_instruction__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 19 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 19]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Compute Metrics L3 Cache Gen8 :: Sampler Texels */ #define bdw__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen8 :: Pixels Failing Tests */ #define bdw__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 10 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank10_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: EU FPU1 Hybrid Instruction */ static float bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 14]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Compute Metrics L3 Cache Gen8 :: GPU Time Elapsed */ #define bdw__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen8 :: Sampler Texels Misses */ #define bdw__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen8 :: CS Threads Dispatched */ #define bdw__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen8 :: SLM Bytes Read */ #define bdw__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 10 IC Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank10_ic_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ UADD 2 UMUL $L3Bank10Accesses UMIN */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 2; uint64_t tmp4 = MIN(tmp3, bdw__compute_l3_cache__l3_bank10_accesses__read(perf, query, accumulator)); return tmp4; } /* Compute Metrics L3 Cache Gen8 :: L3 Bank 10 IC Hits */ static uint64_t bdw__compute_l3_cache__l3_bank10_ic_hits__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ 2 UMUL $L3Bank10IcAccesses UMIN */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = tmp0 * 2; uint64_t tmp2 = MIN(tmp1, bdw__compute_l3_cache__l3_bank10_ic_accesses__read(perf, query, accumulator)); return tmp2; } /* Compute Metrics L3 Cache Gen8 :: GTI Read Throughput */ #define bdw__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen8 :: GTI L3 Throughput */ static uint64_t bdw__compute_l3_cache__gti_l3_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ C 5 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = accumulator[query->c_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Compute Metrics L3 Cache Gen8 :: L3 Bank 00 IC Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank00_ic_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ UADD 2 UMUL $L3Bank00Accesses UMIN */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 2; uint64_t tmp4 = MIN(tmp3, bdw__compute_l3_cache__l3_bank00_accesses__read(perf, query, accumulator)); return tmp4; } /* Compute Metrics L3 Cache Gen8 :: L3 Bank 00 IC Hits */ static uint64_t bdw__compute_l3_cache__l3_bank00_ic_hits__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 1 READ 2 UMUL $L3Bank00IcAccesses UMIN */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = tmp0 * 2; uint64_t tmp2 = MIN(tmp1, bdw__compute_l3_cache__l3_bank00_ic_accesses__read(perf, query, accumulator)); return tmp2; } /* Compute Metrics L3 Cache Gen8 :: L3 Bank 01 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank01_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: GPU Busy */ #define bdw__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen8 :: EU FPU0 Ternary Instruction */ #define bdw__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen8 :: Shader Atomic Memory Accesses */ #define bdw__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen8 :: Rasterized Pixels */ #define bdw__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen8 :: DS Threads Dispatched */ #define bdw__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen8 :: Samples Written */ #define bdw__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen8 :: EU FPU1 Move Instruction */ static float bdw__compute_l3_cache__eu_move_fpu1_instruction__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 20 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 20]; uint64_t tmp1 = tmp0; uint64_t tmp2 = perf->sys_vars.n_eus; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; uint64_t tmp4 = tmp3 * 100; double tmp5 = tmp4; double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(perf, query, accumulator); double tmp7 = tmp6 ? tmp5 / tmp6 : 0; return tmp7; } /* Compute Metrics L3 Cache Gen8 :: EU Stall */ #define bdw__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen8 :: Samples Blended */ #define bdw__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen8 :: Early Depth Test Fails */ #define bdw__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 11 Accesses */ #define bdw__compute_l3_cache__l3_bank11_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 02 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank02_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: L3 Bank 13 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank13_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: Shader Memory Accesses */ #define bdw__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen8 :: HS Threads Dispatched */ #define bdw__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen8 :: GTI Write Throughput */ #define bdw__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen8 :: SLM Bytes Written */ #define bdw__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen8 :: L3 Shader Throughput */ #define bdw__compute_l3_cache__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen8 :: Samples Killed in FS */ #define bdw__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen8 :: L3 Bank 12 Accesses */ static uint64_t bdw__compute_l3_cache__l3_bank12_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen8 :: EU FPU1 Binary Instruction */ #define bdw__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen8 :: EU FPU1 Ternary Instruction */ #define bdw__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen8 :: EU Send Pipe Active */ #define bdw__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Data Port Reads Coalescing Gen8 :: GPU Core Clocks */ #define bdw__data_port_reads_coalescing__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Data Port Reads Coalescing Gen8 :: EU Active */ #define bdw__data_port_reads_coalescing__eu_active__read \ bdw__render_basic__eu_active__read /* Data Port Reads Coalescing Gen8 :: EU Both FPU Pipes Active */ #define bdw__data_port_reads_coalescing__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Data Port Reads Coalescing Gen8 :: EU FPU0 Pipe Active */ #define bdw__data_port_reads_coalescing__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Data Port Reads Coalescing Gen8 :: EU FPU1 Pipe Active */ #define bdw__data_port_reads_coalescing__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Data Port Reads Coalescing Gen8 :: EU AVG IPC Rate */ #define bdw__data_port_reads_coalescing__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Data Port Reads Coalescing Gen8 :: GS Threads Dispatched */ #define bdw__data_port_reads_coalescing__gs_threads__read \ hsw__render_basic__vs_threads__read /* Data Port Reads Coalescing Gen8 :: VS Threads Dispatched */ #define bdw__data_port_reads_coalescing__vs_threads__read \ bdw__render_basic__vs_threads__read /* Data Port Reads Coalescing Gen8 :: FS Threads Dispatched */ #define bdw__data_port_reads_coalescing__ps_threads__read \ bdw__render_basic__ps_threads__read /* Data Port Reads Coalescing Gen8 :: Shader Barrier Messages */ #define bdw__data_port_reads_coalescing__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Data Port Reads Coalescing Gen8 :: Sampler Texels */ #define bdw__data_port_reads_coalescing__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Data Port Reads Coalescing Gen8 :: GPU Time Elapsed */ #define bdw__data_port_reads_coalescing__gpu_time__read \ hsw__render_basic__gpu_time__read /* Data Port Reads Coalescing Gen8 :: AVG GPU Core Frequency */ #define bdw__data_port_reads_coalescing__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Data Port Reads Coalescing Gen8 :: AVG GPU Core Frequency */ #define bdw__data_port_reads_coalescing__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Data Port Reads Coalescing Gen8 :: Sampler Texels Misses */ #define bdw__data_port_reads_coalescing__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Data Port Reads Coalescing Gen8 :: CS Threads Dispatched */ #define bdw__data_port_reads_coalescing__cs_threads__read \ bdw__render_basic__cs_threads__read /* Data Port Reads Coalescing Gen8 :: SLM Bytes Read */ #define bdw__data_port_reads_coalescing__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 64 */ #define bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read \ hsw__compute_extended__eu_typed_atomics0__read /* Data Port Reads Coalescing Gen8 :: Data Port 0 to L3 Data Reads */ #define bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read \ hsw__compute_extended__typed_atomics0__read /* Data Port Reads Coalescing Gen8 :: Data Port 0 to L3 Data Writes */ #define bdw__data_port_reads_coalescing__hdc0_l3_data_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 128 */ #define bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read \ hsw__compute_extended__eu_urb_atomics0__read /* Data Port Reads Coalescing Gen8 :: DS Threads Dispatched */ #define bdw__data_port_reads_coalescing__ds_threads__read \ bdw__render_basic__ds_threads__read /* Data Port Reads Coalescing Gen8 :: EU Thread Occupancy */ #define bdw__data_port_reads_coalescing__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Data Port Reads Coalescing Gen8 :: All Data Port 0 Writes to L3 */ #define bdw__data_port_reads_coalescing__hdc0_l3_writes__read \ hsw__render_basic__gpu_core_clocks__read /* Data Port Reads Coalescing Gen8 :: EU Stall */ #define bdw__data_port_reads_coalescing__eu_stall__read \ bdw__render_basic__eu_stall__read /* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 32 */ #define bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 256 */ #define bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read \ hsw__compute_extended__gpu_clocks__read /* Data Port Reads Coalescing Gen8 :: EuBytesReadPerCacheLine */ static float bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuHdc0Reads32B 32 UMUL $EuHdc0Reads64B 64 UMUL $EuHdc0Reads128B 128 UMUL $EuHdc0Reads256B 256 UMUL UADD UADD UADD $Hdc0L3DataReads FDIV */ uint64_t tmp0 = bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read(perf, query, accumulator) * 32; uint64_t tmp1 = bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read(perf, query, accumulator) * 64; uint64_t tmp2 = bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read(perf, query, accumulator) * 128; uint64_t tmp3 = bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read(perf, query, accumulator) * 256; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = tmp1 + tmp4; uint64_t tmp6 = tmp0 + tmp5; double tmp7 = tmp6; double tmp8 = bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read(perf, query, accumulator); double tmp9 = tmp8 ? tmp7 / tmp8 : 0; return tmp9; } /* Data Port Reads Coalescing Gen8 :: EuDataReadsPerCacheLine */ static float bdw__data_port_reads_coalescing__eu_data_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuBytesReadPerCacheLine 64 FDIV */ double tmp0 = bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read(perf, query, accumulator); double tmp1 = 64; double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Data Port Reads Coalescing Gen8 :: Shader Memory Accesses */ #define bdw__data_port_reads_coalescing__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Data Port Reads Coalescing Gen8 :: HS Threads Dispatched */ #define bdw__data_port_reads_coalescing__hs_threads__read \ bdw__render_basic__hs_threads__read /* Data Port Reads Coalescing Gen8 :: SLM Bytes Written */ #define bdw__data_port_reads_coalescing__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Data Port Reads Coalescing Gen8 :: L3 Shader Throughput */ #define bdw__data_port_reads_coalescing__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Data Port Reads Coalescing Gen8 :: All Data Port 0 Reads from L3 */ static uint64_t bdw__data_port_reads_coalescing__hdc0_l3_reads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ C 2 READ USUB */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = accumulator[query->c_offset + 2]; uint64_t tmp2 = tmp0 - tmp1; return tmp2; } /* Data Port Reads Coalescing Gen8 :: Shader Atomic Memory Accesses */ #define bdw__data_port_reads_coalescing__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Data Port Reads Coalescing Gen8 :: EU Send Pipe Active */ #define bdw__data_port_reads_coalescing__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Data Port Writes Coalescing Gen8 :: GPU Core Clocks */ #define bdw__data_port_writes_coalescing__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Data Port Writes Coalescing Gen8 :: EU Active */ #define bdw__data_port_writes_coalescing__eu_active__read \ bdw__render_basic__eu_active__read /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 128 */ static uint64_t bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ 2 UDIV */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = tmp0; uint64_t tmp2 = 2; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Data Port Writes Coalescing Gen8 :: EU Both FPU Pipes Active */ #define bdw__data_port_writes_coalescing__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Data Port Writes Coalescing Gen8 :: EU FPU0 Pipe Active */ #define bdw__data_port_writes_coalescing__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Data Port Writes Coalescing Gen8 :: EU FPU1 Pipe Active */ #define bdw__data_port_writes_coalescing__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Data Port Writes Coalescing Gen8 :: EU AVG IPC Rate */ #define bdw__data_port_writes_coalescing__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Data Port Writes Coalescing Gen8 :: GS Threads Dispatched */ #define bdw__data_port_writes_coalescing__gs_threads__read \ hsw__render_basic__vs_threads__read /* Data Port Writes Coalescing Gen8 :: VS Threads Dispatched */ #define bdw__data_port_writes_coalescing__vs_threads__read \ bdw__render_basic__vs_threads__read /* Data Port Writes Coalescing Gen8 :: FS Threads Dispatched */ #define bdw__data_port_writes_coalescing__ps_threads__read \ bdw__render_basic__ps_threads__read /* Data Port Writes Coalescing Gen8 :: Shader Barrier Messages */ #define bdw__data_port_writes_coalescing__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Data Port Writes Coalescing Gen8 :: Sampler Texels */ #define bdw__data_port_writes_coalescing__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 32B */ #define bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read \ hsw__compute_extended__eu_untyped_reads0__read /* Data Port Writes Coalescing Gen8 :: GPU Time Elapsed */ #define bdw__data_port_writes_coalescing__gpu_time__read \ hsw__render_basic__gpu_time__read /* Data Port Writes Coalescing Gen8 :: AVG GPU Core Frequency */ #define bdw__data_port_writes_coalescing__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Data Port Writes Coalescing Gen8 :: AVG GPU Core Frequency */ #define bdw__data_port_writes_coalescing__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Data Port Writes Coalescing Gen8 :: Sampler Texels Misses */ #define bdw__data_port_writes_coalescing__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Data Port Writes Coalescing Gen8 :: CS Threads Dispatched */ #define bdw__data_port_writes_coalescing__cs_threads__read \ bdw__render_basic__cs_threads__read /* Data Port Writes Coalescing Gen8 :: SLM Bytes Read */ #define bdw__data_port_writes_coalescing__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 256B */ static uint64_t bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ 2 UDIV */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = tmp0; uint64_t tmp2 = 2; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Data Port Writes Coalescing Gen8 :: Data Port 0 to L3 Data Reads */ #define bdw__data_port_writes_coalescing__hdc0_l3_data_reads__read \ hsw__compute_extended__typed_atomics0__read /* Data Port Writes Coalescing Gen8 :: Data Port 0 to L3 Data Writes */ #define bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 64B */ #define bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read \ hsw__compute_extended__eu_typed_atomics0__read /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 64B */ static uint64_t bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ 2 UDIV */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = tmp0; uint64_t tmp2 = 2; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Data Port Writes Coalescing Gen8 :: DS Threads Dispatched */ #define bdw__data_port_writes_coalescing__ds_threads__read \ bdw__render_basic__ds_threads__read /* Data Port Writes Coalescing Gen8 :: EU Thread Occupancy */ #define bdw__data_port_writes_coalescing__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Data Port Writes Coalescing Gen8 :: All Data Port 0 Writes to L3 */ #define bdw__data_port_writes_coalescing__hdc0_l3_writes__read \ hsw__render_basic__gpu_core_clocks__read /* Data Port Writes Coalescing Gen8 :: EU Stall */ #define bdw__data_port_writes_coalescing__eu_stall__read \ bdw__render_basic__eu_stall__read /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 64B */ static uint64_t bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 1 READ B 4 READ UADD */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = accumulator[query->b_offset + 4]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 128 */ static uint64_t bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ 2 UDIV */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = tmp0; uint64_t tmp2 = 2; uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Data Port Writes Coalescing Gen8 :: EuBytesWrittenPerCacheLine */ static float bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuHdc0Writes32B 32 UMUL $EuHdc0Writes64B 64 UMUL $EuHdc0Writes96B 96 UMUL $EuHdc0Writes128B 128 UMUL $EuHdc0Writes128BSimd16 128 UMUL $EuHdc0Writes256BSimd16 256 UMUL $EuHdc0Writes192B 192 UMUL UADD UADD UADD UADD UADD UADD $Hdc0L3DataWrites FDIV */ uint64_t tmp0 = bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read(perf, query, accumulator) * 32; uint64_t tmp1 = bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read(perf, query, accumulator) * 64; uint64_t tmp2 = bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read(perf, query, accumulator) * 96; uint64_t tmp3 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read(perf, query, accumulator) * 128; uint64_t tmp4 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read(perf, query, accumulator) * 128; uint64_t tmp5 = bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read(perf, query, accumulator) * 256; uint64_t tmp6 = bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read(perf, query, accumulator) * 192; uint64_t tmp7 = tmp5 + tmp6; uint64_t tmp8 = tmp4 + tmp7; uint64_t tmp9 = tmp3 + tmp8; uint64_t tmp10 = tmp2 + tmp9; uint64_t tmp11 = tmp1 + tmp10; uint64_t tmp12 = tmp0 + tmp11; double tmp13 = tmp12; double tmp14 = bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read(perf, query, accumulator); double tmp15 = tmp14 ? tmp13 / tmp14 : 0; return tmp15; } /* Data Port Writes Coalescing Gen8 :: EuDataWritesPerCacheLine */ static float bdw__data_port_writes_coalescing__eu_data_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuBytesWrittenPerCacheLine 64 FDIV */ double tmp0 = bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read(perf, query, accumulator); double tmp1 = 64; double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Data Port Writes Coalescing Gen8 :: Shader Memory Accesses */ #define bdw__data_port_writes_coalescing__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Data Port Writes Coalescing Gen8 :: HS Threads Dispatched */ #define bdw__data_port_writes_coalescing__hs_threads__read \ bdw__render_basic__hs_threads__read /* Data Port Writes Coalescing Gen8 :: SLM Bytes Written */ #define bdw__data_port_writes_coalescing__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Data Port Writes Coalescing Gen8 :: L3 Shader Throughput */ #define bdw__data_port_writes_coalescing__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Data Port Writes Coalescing Gen8 :: All Data Port 0 Reads from L3 */ #define bdw__data_port_writes_coalescing__hdc0_l3_reads__read \ bdw__data_port_reads_coalescing__hdc0_l3_reads__read /* Data Port Writes Coalescing Gen8 :: Shader Atomic Memory Accesses */ #define bdw__data_port_writes_coalescing__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Data Port Writes Coalescing Gen8 :: EU Send Pipe Active */ #define bdw__data_port_writes_coalescing__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define bdw__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define bdw__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define bdw__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define bdw__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define bdw__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define bdw__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define bdw__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define bdw__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define bdw__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define bdw__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define bdw__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ static float bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ C 0 READ USUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = accumulator[query->c_offset + 0]; uint64_t tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: Shader Barrier Messages */ #define bdw__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define bdw__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define bdw__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define bdw__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define bdw__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define bdw__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define bdw__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ static float bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ C 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = accumulator[query->c_offset + 4]; uint64_t tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: CS Threads Dispatched */ #define bdw__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ static float bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ C 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = accumulator[query->c_offset + 6]; uint64_t tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: SLM Bytes Read */ #define bdw__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define bdw__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define bdw__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define bdw__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define bdw__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ static float bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ B 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = accumulator[query->b_offset + 4]; uint64_t tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: Rasterized Pixels */ #define bdw__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define bdw__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define bdw__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define bdw__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define bdw__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define bdw__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define bdw__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define bdw__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define bdw__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ static float bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ B 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = accumulator[query->b_offset + 6]; uint64_t tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: SLM Bytes Written */ #define bdw__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ static uint64_t bdw__hdc_and_sf__l3_shader_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 30 READ A 31 READ $ShaderMemoryAccesses 64 UMUL UADD UADD */ uint64_t tmp0 = accumulator[query->a_offset + 30]; uint64_t tmp1 = accumulator[query->a_offset + 31]; uint64_t tmp2 = bdw__hdc_and_sf__shader_memory_accesses__read(perf, query, accumulator) * 64; uint64_t tmp3 = tmp1 + tmp2; uint64_t tmp4 = tmp0 + tmp3; return tmp4; } /* Metric set HDCAndSF :: Samples Killed in FS */ #define bdw__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ static float bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ C 2 READ USUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = accumulator[query->c_offset + 2]; uint64_t tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define bdw__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define bdw__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define bdw__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice1 L3 Bank1 Stalled */ #define bdw__l3_1__l31_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define bdw__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define bdw__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define bdw__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define bdw__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define bdw__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define bdw__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define bdw__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: FS Threads Dispatched */ #define bdw__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define bdw__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Slice1 L3 Bank0 Stalled */ #define bdw__l3_1__l31_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: Sampler Texels */ #define bdw__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define bdw__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define bdw__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define bdw__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define bdw__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define bdw__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define bdw__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define bdw__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define bdw__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define bdw__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define bdw__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define bdw__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Rasterized Pixels */ #define bdw__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: Slice1 L3 Bank1 Active */ #define bdw__l3_1__l31_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define bdw__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: DS Threads Dispatched */ #define bdw__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define bdw__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define bdw__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Slice1 L3 Bank0 Active */ #define bdw__l3_1__l31_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Samples Blended */ #define bdw__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define bdw__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define bdw__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define bdw__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define bdw__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define bdw__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define bdw__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define bdw__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define bdw__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define bdw__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: Slice0 L3 Bank1 Active */ #define bdw__l3_2__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define bdw__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define bdw__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define bdw__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define bdw__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define bdw__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define bdw__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define bdw__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: Slice0 L3 Bank1 Stalled */ #define bdw__l3_2__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_2 :: FS Threads Dispatched */ #define bdw__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define bdw__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define bdw__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define bdw__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define bdw__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define bdw__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define bdw__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define bdw__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define bdw__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define bdw__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define bdw__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define bdw__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define bdw__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define bdw__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank0 Active */ #define bdw__l3_2__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define bdw__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define bdw__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: Slice0 L3 Bank0 Stalled */ #define bdw__l3_2__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: DS Threads Dispatched */ #define bdw__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define bdw__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define bdw__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define bdw__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define bdw__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define bdw__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define bdw__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define bdw__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define bdw__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define bdw__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define bdw__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define bdw__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define bdw__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define bdw__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define bdw__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define bdw__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define bdw__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define bdw__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define bdw__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define bdw__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define bdw__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define bdw__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define bdw__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define bdw__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define bdw__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define bdw__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define bdw__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define bdw__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define bdw__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define bdw__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define bdw__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define bdw__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define bdw__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define bdw__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define bdw__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define bdw__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Slice1 L3 Bank3 Active */ #define bdw__l3_3__l31_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: Slice1 L3 Bank3 Stalled */ #define bdw__l3_3__l31_bank3_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_3 :: Rasterized Pixels */ #define bdw__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define bdw__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define bdw__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define bdw__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define bdw__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define bdw__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define bdw__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define bdw__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define bdw__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define bdw__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define bdw__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define bdw__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define bdw__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_4 :: GPU Core Clocks */ #define bdw__l3_4__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_4 :: EU Active */ #define bdw__l3_4__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_4 :: EU Both FPU Pipes Active */ #define bdw__l3_4__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_4 :: VS Send Pipe Active */ #define bdw__l3_4__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_4 :: VS FPU1 Pipe Active */ #define bdw__l3_4__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_4 :: GS Threads Dispatched */ #define bdw__l3_4__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_4 :: Early Hi-Depth Test Fails */ #define bdw__l3_4__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_4 :: FS Both FPU Active */ #define bdw__l3_4__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_4 :: VS Threads Dispatched */ #define bdw__l3_4__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_4 :: FS Threads Dispatched */ #define bdw__l3_4__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_4 :: Shader Barrier Messages */ #define bdw__l3_4__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_4 :: Sampler Texels */ #define bdw__l3_4__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_4 :: Pixels Failing Tests */ #define bdw__l3_4__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_4 :: GPU Time Elapsed */ #define bdw__l3_4__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_4 :: AVG GPU Core Frequency */ #define bdw__l3_4__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_4 :: AVG GPU Core Frequency */ #define bdw__l3_4__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_4 :: Sampler Texels Misses */ #define bdw__l3_4__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_4 :: CS Threads Dispatched */ #define bdw__l3_4__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_4 :: SLM Bytes Read */ #define bdw__l3_4__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_4 :: PS FPU1 Pipe Active */ #define bdw__l3_4__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_4 :: Slice0 L3 Bank2 Stalled */ #define bdw__l3_4__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_4 :: PS Send Pipeline Active */ #define bdw__l3_4__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_4 :: VS FPU0 Pipe Active */ #define bdw__l3_4__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_4 :: GPU Busy */ #define bdw__l3_4__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_4 :: Slice1 L3 Bank2 Active */ #define bdw__l3_4__l31_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_4 :: Slice0 L3 Bank2 Active */ #define bdw__l3_4__l30_bank2_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_4 :: Rasterized Pixels */ #define bdw__l3_4__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_4 :: Slice1 L3 Bank2 Stalled */ #define bdw__l3_4__l31_bank2_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_4 :: PS FPU0 Pipe Active */ #define bdw__l3_4__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_4 :: DS Threads Dispatched */ #define bdw__l3_4__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_4 :: Samples Written */ #define bdw__l3_4__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_4 :: EU Stall */ #define bdw__l3_4__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_4 :: Samples Blended */ #define bdw__l3_4__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_4 :: Early Depth Test Fails */ #define bdw__l3_4__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_4 :: Shader Memory Accesses */ #define bdw__l3_4__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_4 :: HS Threads Dispatched */ #define bdw__l3_4__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_4 :: SLM Bytes Written */ #define bdw__l3_4__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_4 :: L3 Shader Throughput */ #define bdw__l3_4__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_4 :: Samples Killed in FS */ #define bdw__l3_4__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_4 :: Shader Atomic Memory Accesses */ #define bdw__l3_4__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define bdw__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define bdw__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define bdw__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */ #define bdw__rasterizer_and_pixel_backend__rasterizer1_input_available__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define bdw__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define bdw__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define bdw__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define bdw__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define bdw__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define bdw__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define bdw__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define bdw__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define bdw__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define bdw__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define bdw__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define bdw__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define bdw__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define bdw__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define bdw__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define bdw__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define bdw__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define bdw__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define bdw__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define bdw__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define bdw__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */ #define bdw__rasterizer_and_pixel_backend__pixel_values1_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */ #define bdw__rasterizer_and_pixel_backend__ps_output1_available__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define bdw__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define bdw__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define bdw__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define bdw__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define bdw__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define bdw__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define bdw__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define bdw__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */ #define bdw__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */ #define bdw__rasterizer_and_pixel_backend__pixel_data1_ready__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define bdw__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define bdw__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define bdw__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define bdw__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define bdw__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define bdw__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define bdw__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler_1 :: GPU Core Clocks */ #define bdw__sampler_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler_1 :: EU Active */ #define bdw__sampler_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler_1 :: EU Both FPU Pipes Active */ #define bdw__sampler_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler_1 :: VS Send Pipe Active */ #define bdw__sampler_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler_1 :: VS FPU1 Pipe Active */ #define bdw__sampler_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler_1 :: GS Threads Dispatched */ #define bdw__sampler_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler_1 :: Slice1 Subslice0 Input Available */ #define bdw__sampler_1__sampler10_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler_1 :: Early Hi-Depth Test Fails */ #define bdw__sampler_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler_1 :: FS Both FPU Active */ #define bdw__sampler_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler_1 :: VS Threads Dispatched */ #define bdw__sampler_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler_1 :: FS Threads Dispatched */ #define bdw__sampler_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler_1 :: Shader Barrier Messages */ #define bdw__sampler_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler_1 :: Sampler Texels */ #define bdw__sampler_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler_1 :: Pixels Failing Tests */ #define bdw__sampler_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler_1 :: Slice1 Subslice2 Sampler Output Ready */ #define bdw__sampler_1__sampler12_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler_1 :: GPU Time Elapsed */ #define bdw__sampler_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler_1 :: AVG GPU Core Frequency */ #define bdw__sampler_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler_1 :: AVG GPU Core Frequency */ #define bdw__sampler_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler_1 :: Sampler Texels Misses */ #define bdw__sampler_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler_1 :: CS Threads Dispatched */ #define bdw__sampler_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler_1 :: SLM Bytes Read */ #define bdw__sampler_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler_1 :: PS FPU1 Pipe Active */ #define bdw__sampler_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler_1 :: PS Send Pipeline Active */ #define bdw__sampler_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler_1 :: VS FPU0 Pipe Active */ #define bdw__sampler_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler_1 :: GPU Busy */ #define bdw__sampler_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler_1 :: Slice1 Subslice1 Input Available */ #define bdw__sampler_1__sampler11_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler_1 :: Rasterized Pixels */ #define bdw__sampler_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler_1 :: PS FPU0 Pipe Active */ #define bdw__sampler_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler_1 :: DS Threads Dispatched */ #define bdw__sampler_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler_1 :: Samples Written */ #define bdw__sampler_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler_1 :: EU Stall */ #define bdw__sampler_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler_1 :: Samples Blended */ #define bdw__sampler_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler_1 :: Early Depth Test Fails */ #define bdw__sampler_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler_1 :: Slice1 Subslice2 Input Available */ #define bdw__sampler_1__sampler12_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler_1 :: Slice1 Subslice0 Sampler Output Ready */ #define bdw__sampler_1__sampler10_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler_1 :: Shader Memory Accesses */ #define bdw__sampler_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler_1 :: Slice1 Subslice1 Sampler Output Ready */ #define bdw__sampler_1__sampler11_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler_1 :: HS Threads Dispatched */ #define bdw__sampler_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler_1 :: SLM Bytes Written */ #define bdw__sampler_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler_1 :: L3 Shader Throughput */ #define bdw__sampler_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler_1 :: Samples Killed in FS */ #define bdw__sampler_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler_1 :: Shader Atomic Memory Accesses */ #define bdw__sampler_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler_2 :: GPU Core Clocks */ #define bdw__sampler_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler_2 :: EU Active */ #define bdw__sampler_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler_2 :: Slice0 Subslice2 Input Available */ #define bdw__sampler_2__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler_2 :: EU Both FPU Pipes Active */ #define bdw__sampler_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler_2 :: VS Send Pipe Active */ #define bdw__sampler_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler_2 :: Slice0 Subslice0 Input Available */ #define bdw__sampler_2__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler_2 :: VS FPU1 Pipe Active */ #define bdw__sampler_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler_2 :: GS Threads Dispatched */ #define bdw__sampler_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler_2 :: Early Hi-Depth Test Fails */ #define bdw__sampler_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler_2 :: FS Both FPU Active */ #define bdw__sampler_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler_2 :: VS Threads Dispatched */ #define bdw__sampler_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler_2 :: Slice0 Subslice2 Sampler Output Ready */ #define bdw__sampler_2__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler_2 :: FS Threads Dispatched */ #define bdw__sampler_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler_2 :: Shader Barrier Messages */ #define bdw__sampler_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler_2 :: Slice0 Subslice1 Input Available */ #define bdw__sampler_2__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler_2 :: Sampler Texels */ #define bdw__sampler_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler_2 :: Pixels Failing Tests */ #define bdw__sampler_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler_2 :: GPU Time Elapsed */ #define bdw__sampler_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler_2 :: AVG GPU Core Frequency */ #define bdw__sampler_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler_2 :: AVG GPU Core Frequency */ #define bdw__sampler_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler_2 :: Sampler Texels Misses */ #define bdw__sampler_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler_2 :: CS Threads Dispatched */ #define bdw__sampler_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler_2 :: SLM Bytes Read */ #define bdw__sampler_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler_2 :: PS FPU1 Pipe Active */ #define bdw__sampler_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler_2 :: PS Send Pipeline Active */ #define bdw__sampler_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler_2 :: VS FPU0 Pipe Active */ #define bdw__sampler_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler_2 :: GPU Busy */ #define bdw__sampler_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler_2 :: Rasterized Pixels */ #define bdw__sampler_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler_2 :: PS FPU0 Pipe Active */ #define bdw__sampler_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler_2 :: DS Threads Dispatched */ #define bdw__sampler_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler_2 :: Samples Written */ #define bdw__sampler_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler_2 :: EU Stall */ #define bdw__sampler_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler_2 :: Samples Blended */ #define bdw__sampler_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler_2 :: Early Depth Test Fails */ #define bdw__sampler_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler_2 :: Slice0 Subslice0 Sampler Output Ready */ #define bdw__sampler_2__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler_2 :: Slice0 Subslice1 Sampler Output Ready */ #define bdw__sampler_2__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler_2 :: Shader Memory Accesses */ #define bdw__sampler_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler_2 :: HS Threads Dispatched */ #define bdw__sampler_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler_2 :: SLM Bytes Written */ #define bdw__sampler_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler_2 :: L3 Shader Throughput */ #define bdw__sampler_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler_2 :: Samples Killed in FS */ #define bdw__sampler_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler_2 :: Shader Atomic Memory Accesses */ #define bdw__sampler_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define bdw__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define bdw__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define bdw__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define bdw__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define bdw__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define bdw__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define bdw__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define bdw__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define bdw__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */ #define bdw__tdl_1__ps_thread11_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define bdw__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice2 */ #define bdw__tdl_1__non_ps_thread12_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define bdw__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define bdw__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define bdw__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */ #define bdw__tdl_1__non_ps_thread10_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define bdw__tdl_1__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define bdw__tdl_1__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define bdw__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define bdw__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define bdw__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define bdw__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define bdw__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define bdw__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define bdw__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define bdw__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define bdw__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define bdw__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define bdw__tdl_1__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define bdw__tdl_1__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_1 :: Rasterized Pixels */ #define bdw__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define bdw__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define bdw__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define bdw__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define bdw__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define bdw__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define bdw__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice2 */ #define bdw__tdl_1__ps_thread12_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */ #define bdw__tdl_1__ps_thread10_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */ #define bdw__tdl_1__non_ps_thread11_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define bdw__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define bdw__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: SLM Bytes Written */ #define bdw__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define bdw__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define bdw__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define bdw__tdl_1__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define bdw__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define bdw__tdl_1__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set TDL_2 :: GPU Core Clocks */ #define bdw__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define bdw__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define bdw__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */ #define bdw__tdl_2__thread_header11_ready_port1__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define bdw__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define bdw__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define bdw__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define bdw__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define bdw__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define bdw__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define bdw__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define bdw__tdl_2__non_ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define bdw__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define bdw__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define bdw__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define bdw__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define bdw__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define bdw__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define bdw__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define bdw__tdl_2__non_ps_thread00_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define bdw__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define bdw__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */ #define bdw__tdl_2__thread_header11_ready_port0__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define bdw__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define bdw__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define bdw__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define bdw__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 0 */ #define bdw__tdl_2__thread_header12_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define bdw__tdl_2__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_2 :: Rasterized Pixels */ #define bdw__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define bdw__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define bdw__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define bdw__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */ #define bdw__tdl_2__thread_header10_ready_port1__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: EU Stall */ #define bdw__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define bdw__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define bdw__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define bdw__tdl_2__ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 1 */ #define bdw__tdl_2__thread_header12_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define bdw__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define bdw__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define bdw__tdl_2__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_2 :: SLM Bytes Written */ #define bdw__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define bdw__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define bdw__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */ #define bdw__tdl_2__thread_header10_ready_port0__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define bdw__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define bdw__tdl_2__non_ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Compute Metrics Extra Gen8 :: GPU Core Clocks */ #define bdw__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen8 :: EU FPU1 Pipe Active */ #define bdw__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen8 :: GPU Time Elapsed */ #define bdw__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen8 :: AVG GPU Core Frequency */ #define bdw__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen8 :: EU FPU1 Pipe Active including Ext Math */ static float bdw__compute_extra__fpu1_active_adjusted__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ C 5 READ C 6 READ FADD C 7 READ FADD C 2 READ FADD C 3 READ FADD C 4 READ FADD 8 FMUL FADD 100 FMUL $EuCoresTotalCount FDIV $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = accumulator[query->c_offset + 5]; uint64_t tmp2 = accumulator[query->c_offset + 6]; double tmp3 = tmp1 + tmp2; uint64_t tmp4 = accumulator[query->c_offset + 7]; double tmp5 = tmp3 + tmp4; uint64_t tmp6 = accumulator[query->c_offset + 2]; double tmp7 = tmp5 + tmp6; uint64_t tmp8 = accumulator[query->c_offset + 3]; double tmp9 = tmp7 + tmp8; uint64_t tmp10 = accumulator[query->c_offset + 4]; double tmp11 = tmp9 + tmp10; double tmp12 = tmp11 * 8; double tmp13 = tmp0 + tmp12; double tmp14 = tmp13 * 100; double tmp15 = tmp14; double tmp16 = perf->sys_vars.n_eus; double tmp17 = tmp16 ? tmp15 / tmp16 : 0; double tmp18 = tmp17; double tmp19 = bdw__compute_extra__gpu_core_clocks__read(perf, query, accumulator); double tmp20 = tmp19 ? tmp18 / tmp19 : 0; return tmp20; } /* Media Vme Pipe Gen8 :: GPU Core Clocks */ #define bdw__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen8 :: EU Active */ #define bdw__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen8 :: EU Both FPU Pipes Active */ #define bdw__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen8 :: GPU Time Elapsed */ #define bdw__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen8 :: AVG GPU Core Frequency */ #define bdw__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen8 :: AVG GPU Core Frequency */ #define bdw__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen8 :: CS Threads Dispatched */ #define bdw__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen8 :: EU Thread Occupancy */ static float bdw__vme_pipe__eu_thread_occupancy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 8 A 10 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 10]; double tmp1 = 8 * tmp0; double tmp2 = tmp1; double tmp3 = perf->sys_vars.eu_threads_count; double tmp4 = tmp3 ? tmp2 / tmp3 : 0; uint64_t tmp5 = tmp4; uint64_t tmp6 = perf->sys_vars.n_eus; uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0; uint64_t tmp8 = tmp7 * 100; double tmp9 = tmp8; double tmp10 = bdw__vme_pipe__gpu_core_clocks__read(perf, query, accumulator); double tmp11 = tmp10 ? tmp9 / tmp10 : 0; return tmp11; } /* Media Vme Pipe Gen8 :: EU Stall */ #define bdw__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen8 :: VME Busy */ static float bdw__vme_pipe__vme_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 3 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 3]; double tmp2 = tmp0 + tmp1; double tmp3 = tmp2; double tmp4 = 2; double tmp5 = tmp4 ? tmp3 / tmp4 : 0; uint64_t tmp6 = tmp5 * 100; double tmp7 = tmp6; double tmp8 = bdw__vme_pipe__gpu_core_clocks__read(perf, query, accumulator); double tmp9 = tmp8 ? tmp7 / tmp8 : 0; return tmp9; } /* Media Vme Pipe Gen8 :: GPU Busy */ #define bdw__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define bdw__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define bdw__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__sf_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define bdw__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define bdw__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define bdw__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define bdw__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define bdw__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define bdw__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define bdw__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* Gpu Rings Busyness :: Vdbox1 Ring Busy */ #define bdw__gpu_busyness__vdbox1_busy__read \ bdw__render_pipe_profile__so_stall__read /* MDAPI testing set Gen8 :: TestCounter7 */ #define bdw__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen8 :: GPU Time Elapsed */ #define bdw__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen8 :: GPU Core Clocks */ #define bdw__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen8 :: AVG GPU Core Frequency */ #define bdw__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen8 :: AVG GPU Core Frequency */ #define bdw__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen8 :: TestCounter8 */ #define bdw__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen8 :: TestCounter4 */ #define bdw__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen8 :: TestCounter5 */ #define bdw__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen8 :: TestCounter6 */ #define bdw__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen8 :: TestCounter3 */ #define bdw__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen8 :: TestCounter0 */ #define bdw__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen8 :: TestCounter1 */ #define bdw__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen8 :: TestCounter2 */ #define bdw__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GS Threads Dispatched */ #define bdw__stc__pma_stall__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define bdw__stc__pma_stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define bdw__stc__pma_stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define bdw__stc__pma_stall__stc_pma_stall__read \ bdw__render_basic__sampler0_busy__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define bdw__stc__pma_stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define bdw__stc__pma_stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set PMA Stall :: HS Threads Dispatched */ #define bdw__stc__pma_stall__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set PMA Stall :: CS Threads Dispatched */ #define bdw__stc__pma_stall__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set PMA Stall :: VS Threads Dispatched */ #define bdw__stc__pma_stall__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set PMA Stall :: DS Threads Dispatched */ #define bdw__stc__pma_stall__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set PMA Stall :: FS Threads Dispatched */ #define bdw__stc__pma_stall__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set PMA Stall :: GPU Busy */ #define bdw__stc__pma_stall__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen8LP :: GPU Core Clocks */ #define chv__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen8LP :: EU Active */ #define chv__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen8LP :: L3 Misses */ #define chv__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen8LP :: GTI L3 Throughput */ #define chv__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen8LP :: EU Both FPU Pipes Active */ #define chv__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen8LP :: VS Send Pipe Active */ #define chv__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen8LP :: Sampler 1 Bottleneck */ #define chv__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen8LP :: VS FPU1 Pipe Active */ #define chv__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen8LP :: GS Threads Dispatched */ #define chv__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen8LP :: L3 Sampler Throughput */ static uint64_t chv__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 29 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 29]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Render Metrics Basic Gen8LP :: Early Hi-Depth Test Fails */ #define chv__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen8LP :: FS Both FPU Active */ #define chv__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen8LP :: VS Threads Dispatched */ #define chv__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen8LP :: FS Threads Dispatched */ #define chv__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen8LP :: Sampler 0 Busy */ #define chv__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen8LP :: Sampler 1 Busy */ #define chv__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen8LP :: Samplers Busy */ static float chv__render_basic__samplers_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ UADD $GpuCoreClocks FDIV 2 FDIV 100 FMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; double tmp3 = tmp2; double tmp4 = chv__render_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp5 = tmp4 ? tmp3 / tmp4 : 0; double tmp6 = tmp5; double tmp7 = 2; double tmp8 = tmp7 ? tmp6 / tmp7 : 0; double tmp9 = tmp8 * 100; return tmp9; } /* Render Metrics Basic Gen8LP :: GTI Fixed Pipe Throughput */ #define chv__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen8LP :: Shader Barrier Messages */ #define chv__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen8LP :: Sampler 0 Bottleneck */ #define chv__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen8LP :: Sampler Texels */ #define chv__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen8LP :: Pixels Failing Tests */ #define chv__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen8LP :: GPU Time Elapsed */ #define chv__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen8LP :: AVG GPU Core Frequency */ #define chv__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen8LP :: AVG GPU Core Frequency */ #define chv__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen8LP :: Sampler Texels Misses */ #define chv__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen8LP :: CS Threads Dispatched */ #define chv__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen8LP :: Shader Memory Accesses */ #define chv__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen8LP :: SLM Bytes Read */ #define chv__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen8LP :: GTI Read Throughput */ #define chv__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen8LP :: PS FPU1 Pipe Active */ #define chv__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen8LP :: PS Send Pipeline Active */ #define chv__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen8LP :: Rasterized Pixels */ #define chv__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen8LP :: GPU Busy */ #define chv__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen8LP :: GTI Depth Throughput */ #define chv__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen8LP :: VS FPU0 Pipe Active */ #define chv__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen8LP :: PS FPU0 Pipe Active */ #define chv__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen8LP :: DS Threads Dispatched */ #define chv__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen8LP :: Samples Written */ #define chv__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen8LP :: EU Stall */ #define chv__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen8LP :: Samples Blended */ #define chv__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen8LP :: Early Depth Test Fails */ #define chv__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen8LP :: Samplers Bottleneck */ #define chv__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen8LP :: GTI HDC TLB Lookup Throughput */ #define chv__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen8LP :: GTI RCC Throughput */ #define chv__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen8LP :: HS Threads Dispatched */ #define chv__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen8LP :: GTI Write Throughput */ #define chv__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen8LP :: SLM Bytes Written */ #define chv__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen8LP :: L3 Shader Throughput */ #define chv__render_basic__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Render Metrics Basic Gen8LP :: Samples Killed in FS */ #define chv__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen8LP :: Shader Atomic Memory Accesses */ #define chv__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen8LP :: GPU Core Clocks */ #define chv__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen8LP :: EU Active */ #define chv__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen8LP :: Untyped Bytes Read */ static uint64_t chv__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Compute Metrics Basic Gen8LP :: EU Both FPU Pipes Active */ #define chv__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen8LP :: Typed Bytes Written */ static uint64_t chv__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ B 3 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = accumulator[query->b_offset + 3]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Compute Metrics Basic Gen8LP :: EU FPU0 Pipe Active */ #define chv__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen8LP :: EU FPU1 Pipe Active */ #define chv__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen8LP :: EU AVG IPC Rate */ #define chv__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen8LP :: GS Threads Dispatched */ #define chv__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen8LP :: Early Hi-Depth Test Fails */ #define chv__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen8LP :: VS Threads Dispatched */ #define chv__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen8LP :: FS Threads Dispatched */ #define chv__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen8LP :: Shader Barrier Messages */ #define chv__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen8LP :: Sampler Texels */ #define chv__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen8LP :: Pixels Failing Tests */ #define chv__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen8LP :: GPU Time Elapsed */ #define chv__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen8LP :: AVG GPU Core Frequency */ #define chv__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen8LP :: AVG GPU Core Frequency */ #define chv__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen8LP :: Sampler Texels Misses */ #define chv__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen8LP :: CS Threads Dispatched */ #define chv__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen8LP :: Shader Memory Accesses */ #define chv__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen8LP :: SLM Bytes Read */ #define chv__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen8LP :: GTI Read Throughput */ #define chv__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_depth_throughput__read /* Compute Metrics Basic Gen8LP :: GTI Ring Throughput */ static uint64_t chv__compute_basic__gti_ring_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ 128 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = tmp0 * 128; return tmp1; } /* Compute Metrics Basic Gen8LP :: Untyped Writes */ #define chv__compute_basic__untyped_bytes_written__read \ hsw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen8LP :: GPU Busy */ #define chv__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen8LP :: Rasterized Pixels */ #define chv__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen8LP :: Typed Bytes Read */ static uint64_t chv__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 64; return tmp3; } /* Compute Metrics Basic Gen8LP :: GTI Read-Only Stall */ #define chv__compute_basic__gti_ro_stall__read \ bdw__render_pipe_profile__so_stall__read /* Compute Metrics Basic Gen8LP :: DS Threads Dispatched */ #define chv__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen8LP :: EU Thread Occupancy */ #define chv__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen8LP :: GTI Read-Write Stall */ #define chv__compute_basic__gti_rw_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Compute Metrics Basic Gen8LP :: EU Stall */ #define chv__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen8LP :: Samples Blended */ #define chv__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen8LP :: Early Depth Test Fails */ #define chv__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen8LP :: HS Threads Dispatched */ #define chv__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen8LP :: GTI Write Throughput */ #define chv__compute_basic__gti_write_throughput__read \ hsw__render_basic__gti_vf_throughput__read /* Compute Metrics Basic Gen8LP :: SLM Bytes Written */ #define chv__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen8LP :: L3 Shader Throughput */ #define chv__compute_basic__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Compute Metrics Basic Gen8LP :: Samples Killed in FS */ #define chv__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen8LP :: Samples Written */ #define chv__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen8LP :: Shader Atomic Memory Accesses */ #define chv__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen8LP :: EU Send Pipe Active */ #define chv__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */ #define chv__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile :: EU Active */ #define chv__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */ #define chv__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */ #define chv__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */ #define chv__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */ #define chv__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */ #define chv__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */ #define chv__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */ #define chv__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */ #define chv__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: HS Stall */ #define chv__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */ #define chv__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile :: Sampler Texels */ #define chv__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */ #define chv__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */ #define chv__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ #define chv__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ #define chv__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */ #define chv__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */ #define chv__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */ #define chv__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */ #define chv__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */ #define chv__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: Sampler Accesses */ #define chv__render_pipe_profile__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Render Metrics for 3D Pipeline Profile :: SF Stall */ #define chv__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile :: GPU Busy */ #define chv__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */ #define chv__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile :: CL Stall */ #define chv__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */ #define chv__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */ #define chv__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */ #define chv__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile :: Samples Written */ #define chv__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */ #define chv__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: EU Stall */ #define chv__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */ #define chv__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: DS Stall */ #define chv__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile :: Early Depth Bottleneck */ #define chv__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile :: Samples Blended */ #define chv__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */ #define chv__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */ #define chv__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */ #define chv__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */ #define chv__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */ #define chv__render_pipe_profile__l3_shader_throughput__read \ bdw__render_basic__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */ #define chv__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile :: SO Stall */ #define chv__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */ #define chv__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define chv__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define chv__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define chv__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define chv__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define chv__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define chv__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define chv__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define chv__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define chv__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define chv__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define chv__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define chv__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define chv__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define chv__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define chv__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define chv__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define chv__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define chv__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define chv__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define chv__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define chv__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define chv__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define chv__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define chv__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define chv__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define chv__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define chv__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define chv__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define chv__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define chv__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define chv__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define chv__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define chv__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define chv__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define chv__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define chv__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define chv__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define chv__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define chv__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define chv__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define chv__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define chv__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define chv__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define chv__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define chv__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice1 L3 Bank1 Stalled */ #define chv__l3_1__l31_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define chv__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define chv__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define chv__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define chv__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define chv__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define chv__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define chv__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: FS Threads Dispatched */ #define chv__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define chv__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Slice1 L3 Bank0 Stalled */ #define chv__l3_1__l31_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: Sampler Texels */ #define chv__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define chv__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define chv__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define chv__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define chv__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define chv__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define chv__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define chv__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define chv__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define chv__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define chv__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define chv__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Rasterized Pixels */ #define chv__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: Slice1 L3 Bank1 Active */ #define chv__l3_1__l31_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define chv__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: DS Threads Dispatched */ #define chv__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define chv__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define chv__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Slice1 L3 Bank0 Active */ #define chv__l3_1__l31_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Samples Blended */ #define chv__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define chv__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define chv__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define chv__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define chv__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define chv__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define chv__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define chv__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define chv__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define chv__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: Slice0 L3 Bank1 Active */ #define chv__l3_2__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define chv__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define chv__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define chv__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define chv__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define chv__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define chv__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define chv__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: Slice0 L3 Bank1 Stalled */ #define chv__l3_2__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_2 :: FS Threads Dispatched */ #define chv__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define chv__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define chv__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define chv__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define chv__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define chv__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define chv__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define chv__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define chv__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define chv__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define chv__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define chv__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define chv__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define chv__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank0 Active */ #define chv__l3_2__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define chv__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define chv__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: Slice0 L3 Bank0 Stalled */ #define chv__l3_2__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: DS Threads Dispatched */ #define chv__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define chv__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define chv__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define chv__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define chv__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define chv__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define chv__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define chv__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define chv__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define chv__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define chv__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define chv__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define chv__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define chv__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define chv__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define chv__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define chv__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define chv__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define chv__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define chv__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define chv__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define chv__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define chv__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define chv__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define chv__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define chv__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define chv__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define chv__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define chv__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define chv__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define chv__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define chv__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define chv__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define chv__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define chv__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define chv__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Slice1 L3 Bank3 Active */ #define chv__l3_3__l31_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: Slice1 L3 Bank3 Stalled */ #define chv__l3_3__l31_bank3_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_3 :: Rasterized Pixels */ #define chv__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define chv__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define chv__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define chv__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define chv__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define chv__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define chv__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define chv__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define chv__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define chv__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define chv__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define chv__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define chv__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_4 :: GPU Core Clocks */ #define chv__l3_4__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_4 :: EU Active */ #define chv__l3_4__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_4 :: EU Both FPU Pipes Active */ #define chv__l3_4__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_4 :: VS Send Pipe Active */ #define chv__l3_4__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_4 :: VS FPU1 Pipe Active */ #define chv__l3_4__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_4 :: GS Threads Dispatched */ #define chv__l3_4__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_4 :: Early Hi-Depth Test Fails */ #define chv__l3_4__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_4 :: FS Both FPU Active */ #define chv__l3_4__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_4 :: VS Threads Dispatched */ #define chv__l3_4__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_4 :: FS Threads Dispatched */ #define chv__l3_4__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_4 :: Shader Barrier Messages */ #define chv__l3_4__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_4 :: Sampler Texels */ #define chv__l3_4__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_4 :: Pixels Failing Tests */ #define chv__l3_4__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_4 :: GPU Time Elapsed */ #define chv__l3_4__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_4 :: AVG GPU Core Frequency */ #define chv__l3_4__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_4 :: AVG GPU Core Frequency */ #define chv__l3_4__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_4 :: Sampler Texels Misses */ #define chv__l3_4__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_4 :: CS Threads Dispatched */ #define chv__l3_4__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_4 :: SLM Bytes Read */ #define chv__l3_4__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_4 :: PS FPU1 Pipe Active */ #define chv__l3_4__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_4 :: Slice0 L3 Bank2 Stalled */ #define chv__l3_4__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_4 :: PS Send Pipeline Active */ #define chv__l3_4__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_4 :: VS FPU0 Pipe Active */ #define chv__l3_4__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_4 :: GPU Busy */ #define chv__l3_4__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_4 :: Slice1 L3 Bank2 Active */ #define chv__l3_4__l31_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_4 :: Slice0 L3 Bank2 Active */ #define chv__l3_4__l30_bank2_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_4 :: Rasterized Pixels */ #define chv__l3_4__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_4 :: Slice1 L3 Bank2 Stalled */ #define chv__l3_4__l31_bank2_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_4 :: PS FPU0 Pipe Active */ #define chv__l3_4__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_4 :: DS Threads Dispatched */ #define chv__l3_4__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_4 :: Samples Written */ #define chv__l3_4__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_4 :: EU Stall */ #define chv__l3_4__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_4 :: Samples Blended */ #define chv__l3_4__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_4 :: Early Depth Test Fails */ #define chv__l3_4__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_4 :: Shader Memory Accesses */ #define chv__l3_4__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_4 :: HS Threads Dispatched */ #define chv__l3_4__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_4 :: SLM Bytes Written */ #define chv__l3_4__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_4 :: L3 Shader Throughput */ #define chv__l3_4__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_4 :: Samples Killed in FS */ #define chv__l3_4__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_4 :: Shader Atomic Memory Accesses */ #define chv__l3_4__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define chv__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define chv__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define chv__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */ #define chv__rasterizer_and_pixel_backend__rasterizer1_input_available__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define chv__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define chv__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define chv__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define chv__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define chv__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define chv__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define chv__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define chv__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define chv__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define chv__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define chv__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define chv__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define chv__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define chv__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define chv__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define chv__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define chv__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define chv__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define chv__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define chv__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define chv__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */ #define chv__rasterizer_and_pixel_backend__pixel_values1_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */ #define chv__rasterizer_and_pixel_backend__ps_output1_available__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define chv__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define chv__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define chv__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define chv__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define chv__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define chv__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define chv__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define chv__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */ #define chv__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */ #define chv__rasterizer_and_pixel_backend__pixel_data1_ready__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define chv__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define chv__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define chv__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define chv__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define chv__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define chv__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define chv__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler_1 :: GPU Core Clocks */ #define chv__sampler_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler_1 :: EU Active */ #define chv__sampler_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler_1 :: EU Both FPU Pipes Active */ #define chv__sampler_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler_1 :: VS Send Pipe Active */ #define chv__sampler_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler_1 :: VS FPU1 Pipe Active */ #define chv__sampler_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler_1 :: GS Threads Dispatched */ #define chv__sampler_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler_1 :: Slice1 Subslice0 Input Available */ #define chv__sampler_1__sampler10_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler_1 :: Early Hi-Depth Test Fails */ #define chv__sampler_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler_1 :: FS Both FPU Active */ #define chv__sampler_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler_1 :: VS Threads Dispatched */ #define chv__sampler_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler_1 :: FS Threads Dispatched */ #define chv__sampler_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler_1 :: Shader Barrier Messages */ #define chv__sampler_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler_1 :: Sampler Texels */ #define chv__sampler_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler_1 :: Pixels Failing Tests */ #define chv__sampler_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler_1 :: Slice1 Subslice2 Sampler Output Ready */ #define chv__sampler_1__sampler12_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler_1 :: GPU Time Elapsed */ #define chv__sampler_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler_1 :: AVG GPU Core Frequency */ #define chv__sampler_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler_1 :: AVG GPU Core Frequency */ #define chv__sampler_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler_1 :: Sampler Texels Misses */ #define chv__sampler_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler_1 :: CS Threads Dispatched */ #define chv__sampler_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler_1 :: SLM Bytes Read */ #define chv__sampler_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler_1 :: PS FPU1 Pipe Active */ #define chv__sampler_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler_1 :: PS Send Pipeline Active */ #define chv__sampler_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler_1 :: VS FPU0 Pipe Active */ #define chv__sampler_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler_1 :: GPU Busy */ #define chv__sampler_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler_1 :: Slice1 Subslice1 Input Available */ #define chv__sampler_1__sampler11_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler_1 :: Rasterized Pixels */ #define chv__sampler_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler_1 :: PS FPU0 Pipe Active */ #define chv__sampler_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler_1 :: DS Threads Dispatched */ #define chv__sampler_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler_1 :: Samples Written */ #define chv__sampler_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler_1 :: EU Stall */ #define chv__sampler_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler_1 :: Samples Blended */ #define chv__sampler_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler_1 :: Early Depth Test Fails */ #define chv__sampler_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler_1 :: Slice1 Subslice2 Input Available */ #define chv__sampler_1__sampler12_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler_1 :: Slice1 Subslice0 Sampler Output Ready */ #define chv__sampler_1__sampler10_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler_1 :: Shader Memory Accesses */ #define chv__sampler_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler_1 :: Slice1 Subslice1 Sampler Output Ready */ #define chv__sampler_1__sampler11_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler_1 :: HS Threads Dispatched */ #define chv__sampler_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler_1 :: SLM Bytes Written */ #define chv__sampler_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler_1 :: L3 Shader Throughput */ #define chv__sampler_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler_1 :: Samples Killed in FS */ #define chv__sampler_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler_1 :: Shader Atomic Memory Accesses */ #define chv__sampler_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler_2 :: GPU Core Clocks */ #define chv__sampler_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler_2 :: EU Active */ #define chv__sampler_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler_2 :: Slice0 Subslice2 Input Available */ #define chv__sampler_2__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler_2 :: EU Both FPU Pipes Active */ #define chv__sampler_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler_2 :: VS Send Pipe Active */ #define chv__sampler_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler_2 :: Slice0 Subslice0 Input Available */ #define chv__sampler_2__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler_2 :: VS FPU1 Pipe Active */ #define chv__sampler_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler_2 :: GS Threads Dispatched */ #define chv__sampler_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler_2 :: Early Hi-Depth Test Fails */ #define chv__sampler_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler_2 :: FS Both FPU Active */ #define chv__sampler_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler_2 :: VS Threads Dispatched */ #define chv__sampler_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler_2 :: Slice0 Subslice2 Sampler Output Ready */ #define chv__sampler_2__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler_2 :: FS Threads Dispatched */ #define chv__sampler_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler_2 :: Shader Barrier Messages */ #define chv__sampler_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler_2 :: Slice0 Subslice1 Input Available */ #define chv__sampler_2__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler_2 :: Sampler Texels */ #define chv__sampler_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler_2 :: Pixels Failing Tests */ #define chv__sampler_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler_2 :: GPU Time Elapsed */ #define chv__sampler_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler_2 :: AVG GPU Core Frequency */ #define chv__sampler_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler_2 :: AVG GPU Core Frequency */ #define chv__sampler_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler_2 :: Sampler Texels Misses */ #define chv__sampler_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler_2 :: CS Threads Dispatched */ #define chv__sampler_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler_2 :: SLM Bytes Read */ #define chv__sampler_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler_2 :: PS FPU1 Pipe Active */ #define chv__sampler_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler_2 :: PS Send Pipeline Active */ #define chv__sampler_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler_2 :: VS FPU0 Pipe Active */ #define chv__sampler_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler_2 :: GPU Busy */ #define chv__sampler_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler_2 :: Rasterized Pixels */ #define chv__sampler_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler_2 :: PS FPU0 Pipe Active */ #define chv__sampler_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler_2 :: DS Threads Dispatched */ #define chv__sampler_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler_2 :: Samples Written */ #define chv__sampler_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler_2 :: EU Stall */ #define chv__sampler_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler_2 :: Samples Blended */ #define chv__sampler_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler_2 :: Early Depth Test Fails */ #define chv__sampler_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler_2 :: Slice0 Subslice0 Sampler Output Ready */ #define chv__sampler_2__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler_2 :: Slice0 Subslice1 Sampler Output Ready */ #define chv__sampler_2__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler_2 :: Shader Memory Accesses */ #define chv__sampler_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler_2 :: HS Threads Dispatched */ #define chv__sampler_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler_2 :: SLM Bytes Written */ #define chv__sampler_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler_2 :: L3 Shader Throughput */ #define chv__sampler_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler_2 :: Samples Killed in FS */ #define chv__sampler_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler_2 :: Shader Atomic Memory Accesses */ #define chv__sampler_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define chv__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define chv__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define chv__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define chv__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define chv__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define chv__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define chv__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define chv__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define chv__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */ #define chv__tdl_1__ps_thread11_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define chv__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice2 */ #define chv__tdl_1__non_ps_thread12_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define chv__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define chv__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define chv__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */ #define chv__tdl_1__non_ps_thread10_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define chv__tdl_1__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define chv__tdl_1__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define chv__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define chv__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define chv__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define chv__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define chv__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define chv__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define chv__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define chv__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define chv__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define chv__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define chv__tdl_1__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define chv__tdl_1__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_1 :: Rasterized Pixels */ #define chv__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define chv__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define chv__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define chv__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define chv__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define chv__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define chv__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice2 */ #define chv__tdl_1__ps_thread12_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */ #define chv__tdl_1__ps_thread10_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */ #define chv__tdl_1__non_ps_thread11_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define chv__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define chv__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: SLM Bytes Written */ #define chv__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define chv__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define chv__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define chv__tdl_1__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define chv__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define chv__tdl_1__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set TDL_2 :: GPU Core Clocks */ #define chv__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define chv__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define chv__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */ #define chv__tdl_2__thread_header11_ready_port1__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define chv__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define chv__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define chv__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define chv__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define chv__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define chv__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define chv__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define chv__tdl_2__non_ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define chv__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define chv__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define chv__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define chv__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define chv__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define chv__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define chv__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define chv__tdl_2__non_ps_thread00_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define chv__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define chv__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */ #define chv__tdl_2__thread_header11_ready_port0__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define chv__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define chv__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define chv__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define chv__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 0 */ #define chv__tdl_2__thread_header12_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define chv__tdl_2__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_2 :: Rasterized Pixels */ #define chv__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define chv__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define chv__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define chv__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */ #define chv__tdl_2__thread_header10_ready_port1__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: EU Stall */ #define chv__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define chv__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define chv__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define chv__tdl_2__ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 1 */ #define chv__tdl_2__thread_header12_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define chv__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define chv__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define chv__tdl_2__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_2 :: SLM Bytes Written */ #define chv__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define chv__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define chv__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */ #define chv__tdl_2__thread_header10_ready_port0__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define chv__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define chv__tdl_2__non_ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* MDAPI testing set Gen8LP :: TestCounter7 */ #define chv__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen8LP :: GPU Time Elapsed */ #define chv__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen8LP :: GPU Core Clocks */ #define chv__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen8LP :: AVG GPU Core Frequency */ #define chv__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen8LP :: AVG GPU Core Frequency */ #define chv__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen8LP :: TestCounter8 */ #define chv__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen8LP :: TestCounter4 */ #define chv__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen8LP :: TestCounter5 */ #define chv__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen8LP :: TestCounter6 */ #define chv__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen8LP :: TestCounter3 */ #define chv__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen8LP :: TestCounter0 */ #define chv__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen8LP :: TestCounter1 */ #define chv__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen8LP :: TestCounter2 */ #define chv__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define sklgt2__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define sklgt2__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define sklgt2__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define sklgt2__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define sklgt2__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ static uint64_t sklgt2__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ 8 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = tmp0 * 8; return tmp1; } /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define sklgt2__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define sklgt2__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define sklgt2__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define sklgt2__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ static uint64_t sklgt2__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses 64 UMUL */ uint64_t tmp0 = sklgt2__render_basic__sampler_l1_misses__read(perf, query, accumulator) * 64; return tmp0; } /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define sklgt2__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define sklgt2__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define sklgt2__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define sklgt2__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define sklgt2__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define sklgt2__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define sklgt2__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define sklgt2__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define sklgt2__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define sklgt2__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define sklgt2__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define sklgt2__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define sklgt2__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt2__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt2__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define sklgt2__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define sklgt2__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define sklgt2__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ static uint64_t sklgt2__render_basic__l3_lookups__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ uint64_t tmp0 = sklgt2__render_basic__sampler_l1_misses__read(perf, query, accumulator) + sklgt2__render_basic__shader_memory_accesses__read(perf, query, accumulator); return tmp0; } /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define sklgt2__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define sklgt2__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define sklgt2__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define sklgt2__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define sklgt2__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define sklgt2__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define sklgt2__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define sklgt2__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define sklgt2__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define sklgt2__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define sklgt2__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define sklgt2__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define sklgt2__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define sklgt2__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define sklgt2__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define sklgt2__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define sklgt2__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define sklgt2__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define sklgt2__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define sklgt2__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define sklgt2__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define sklgt2__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define sklgt2__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define sklgt2__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define sklgt2__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define sklgt2__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define sklgt2__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define sklgt2__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define sklgt2__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define sklgt2__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define sklgt2__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define sklgt2__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define sklgt2__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define sklgt2__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define sklgt2__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define sklgt2__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define sklgt2__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define sklgt2__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define sklgt2__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define sklgt2__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define sklgt2__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define sklgt2__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define sklgt2__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define sklgt2__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define sklgt2__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define sklgt2__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define sklgt2__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define sklgt2__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define sklgt2__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define sklgt2__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define sklgt2__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define sklgt2__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define sklgt2__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define sklgt2__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define sklgt2__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define sklgt2__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define sklgt2__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define sklgt2__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define sklgt2__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define sklgt2__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define sklgt2__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define sklgt2__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define sklgt2__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define sklgt2__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define sklgt2__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define sklgt2__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define sklgt2__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define sklgt2__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define sklgt2__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define sklgt2__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define sklgt2__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define sklgt2__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define sklgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define sklgt2__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define sklgt2__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define sklgt2__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define sklgt2__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define sklgt2__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define sklgt2__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define sklgt2__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define sklgt2__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define sklgt2__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define sklgt2__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define sklgt2__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define sklgt2__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define sklgt2__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define sklgt2__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define sklgt2__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define sklgt2__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define sklgt2__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define sklgt2__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define sklgt2__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define sklgt2__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define sklgt2__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define sklgt2__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define sklgt2__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define sklgt2__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define sklgt2__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define sklgt2__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define sklgt2__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define sklgt2__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define sklgt2__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define sklgt2__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define sklgt2__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define sklgt2__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define sklgt2__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define sklgt2__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define sklgt2__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define sklgt2__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define sklgt2__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define sklgt2__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define sklgt2__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define sklgt2__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define sklgt2__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define sklgt2__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define sklgt2__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define sklgt2__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt2__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt2__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define sklgt2__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define sklgt2__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define sklgt2__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define sklgt2__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define sklgt2__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define sklgt2__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define sklgt2__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define sklgt2__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define sklgt2__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define sklgt2__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define sklgt2__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define sklgt2__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define sklgt2__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define sklgt2__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define sklgt2__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define sklgt2__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define sklgt2__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define sklgt2__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define sklgt2__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define sklgt2__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define sklgt2__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define sklgt2__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define sklgt2__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define sklgt2__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define sklgt2__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define sklgt2__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define sklgt2__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define sklgt2__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define sklgt2__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define sklgt2__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define sklgt2__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define sklgt2__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define sklgt2__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define sklgt2__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define sklgt2__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define sklgt2__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define sklgt2__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define sklgt2__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define sklgt2__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define sklgt2__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define sklgt2__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define sklgt2__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define sklgt2__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt2__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt2__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define sklgt2__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define sklgt2__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define sklgt2__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define sklgt2__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define sklgt2__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define sklgt2__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define sklgt2__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define sklgt2__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define sklgt2__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define sklgt2__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define sklgt2__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define sklgt2__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define sklgt2__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define sklgt2__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define sklgt2__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define sklgt2__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define sklgt2__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define sklgt2__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define sklgt2__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define sklgt2__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define sklgt2__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define sklgt2__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define sklgt2__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define sklgt2__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define sklgt2__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define sklgt2__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define sklgt2__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define sklgt2__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define sklgt2__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define sklgt2__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define sklgt2__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define sklgt2__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define sklgt2__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define sklgt2__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define sklgt2__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define sklgt2__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define sklgt2__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define sklgt2__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define sklgt2__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define sklgt2__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define sklgt2__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define sklgt2__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define sklgt2__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define sklgt2__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define sklgt2__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define sklgt2__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define sklgt2__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define sklgt2__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define sklgt2__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define sklgt2__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define sklgt2__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define sklgt2__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define sklgt2__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define sklgt2__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define sklgt2__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define sklgt2__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define sklgt2__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define sklgt2__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define sklgt2__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ static uint64_t sklgt2__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ C 1 READ B 2 READ B 3 READ UADD UADD UADD 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; uint64_t tmp2 = accumulator[query->b_offset + 2]; uint64_t tmp3 = accumulator[query->b_offset + 3]; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = tmp1 + tmp4; uint64_t tmp6 = tmp0 + tmp5; uint64_t tmp7 = tmp6 * 2; return tmp7; } /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define sklgt2__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define sklgt2__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define sklgt2__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define sklgt2__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define sklgt2__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define sklgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define sklgt2__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define sklgt2__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define sklgt2__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define sklgt2__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define sklgt2__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define sklgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define sklgt2__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define sklgt2__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define sklgt2__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define sklgt2__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define sklgt2__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define sklgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define sklgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define sklgt2__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define sklgt2__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define sklgt2__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define sklgt2__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define sklgt2__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define sklgt2__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define sklgt2__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define sklgt2__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define sklgt2__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define sklgt2__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define sklgt2__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define sklgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define sklgt2__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define sklgt2__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define sklgt2__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define sklgt2__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define sklgt2__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define sklgt2__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define sklgt2__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define sklgt2__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define sklgt2__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define sklgt2__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ static uint64_t sklgt2__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Accesses 64 UMUL */ uint64_t tmp0 = sklgt2__compute_l3_cache__l3_accesses__read(perf, query, accumulator) * 64; return tmp0; } /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define sklgt2__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define sklgt2__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define sklgt2__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define sklgt2__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define sklgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define sklgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define sklgt2__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define sklgt2__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define sklgt2__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define sklgt2__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define sklgt2__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define sklgt2__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define sklgt2__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define sklgt2__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define sklgt2__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define sklgt2__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define sklgt2__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define sklgt2__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define sklgt2__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define sklgt2__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define sklgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define sklgt2__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define sklgt2__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define sklgt2__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define sklgt2__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define sklgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define sklgt2__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define sklgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define sklgt2__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define sklgt2__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define sklgt2__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define sklgt2__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define sklgt2__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define sklgt2__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define sklgt2__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define sklgt2__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define sklgt2__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define sklgt2__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define sklgt2__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define sklgt2__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define sklgt2__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define sklgt2__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define sklgt2__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define sklgt2__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define sklgt2__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define sklgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define sklgt2__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define sklgt2__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define sklgt2__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define sklgt2__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define sklgt2__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define sklgt2__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define sklgt2__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define sklgt2__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define sklgt2__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define sklgt2__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define sklgt2__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define sklgt2__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define sklgt2__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define sklgt2__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define sklgt2__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define sklgt2__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define sklgt2__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define sklgt2__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define sklgt2__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define sklgt2__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define sklgt2__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define sklgt2__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define sklgt2__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define sklgt2__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define sklgt2__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define sklgt2__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define sklgt2__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define sklgt2__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define sklgt2__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define sklgt2__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define sklgt2__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define sklgt2__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define sklgt2__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define sklgt2__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define sklgt2__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define sklgt2__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define sklgt2__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define sklgt2__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define sklgt2__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define sklgt2__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define sklgt2__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define sklgt2__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define sklgt2__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define sklgt2__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define sklgt2__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define sklgt2__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define sklgt2__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define sklgt2__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define sklgt2__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define sklgt2__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define sklgt2__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define sklgt2__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define sklgt2__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define sklgt2__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define sklgt2__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define sklgt2__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define sklgt2__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define sklgt2__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define sklgt2__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define sklgt2__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define sklgt2__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define sklgt2__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define sklgt2__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define sklgt2__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define sklgt2__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define sklgt2__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define sklgt2__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define sklgt2__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define sklgt2__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define sklgt2__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define sklgt2__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define sklgt2__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define sklgt2__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define sklgt2__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define sklgt2__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define sklgt2__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define sklgt2__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define sklgt2__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define sklgt2__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define sklgt2__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define sklgt2__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define sklgt2__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define sklgt2__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define sklgt2__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define sklgt2__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define sklgt2__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define sklgt2__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define sklgt2__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define sklgt2__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define sklgt2__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define sklgt2__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define sklgt2__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define sklgt2__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define sklgt2__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define sklgt2__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define sklgt2__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define sklgt2__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define sklgt2__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define sklgt2__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define sklgt2__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define sklgt2__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define sklgt2__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define sklgt2__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define sklgt2__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define sklgt2__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define sklgt2__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define sklgt2__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define sklgt2__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define sklgt2__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define sklgt2__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define sklgt2__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define sklgt2__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define sklgt2__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define sklgt2__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define sklgt2__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define sklgt2__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define sklgt2__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define sklgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define sklgt2__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define sklgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define sklgt2__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define sklgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define sklgt2__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define sklgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define sklgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define sklgt2__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define sklgt2__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define sklgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define sklgt2__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define sklgt2__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define sklgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define sklgt2__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define sklgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define sklgt2__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define sklgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define sklgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define sklgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define sklgt2__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define sklgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define sklgt2__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define sklgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define sklgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define sklgt2__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define sklgt2__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define sklgt2__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define sklgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define sklgt2__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define sklgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define sklgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define sklgt2__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define sklgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define sklgt2__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define sklgt2__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define sklgt2__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define sklgt2__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define sklgt2__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define sklgt2__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define sklgt2__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define sklgt2__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define sklgt2__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define sklgt2__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define sklgt2__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define sklgt2__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define sklgt2__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define sklgt2__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define sklgt2__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define sklgt2__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define sklgt2__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define sklgt2__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define sklgt2__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define sklgt2__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define sklgt2__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define sklgt2__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define sklgt2__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define sklgt2__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define sklgt2__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define sklgt2__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define sklgt2__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define sklgt2__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define sklgt2__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define sklgt2__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define sklgt2__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define sklgt2__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define sklgt2__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define sklgt2__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define sklgt2__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define sklgt2__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define sklgt2__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define sklgt2__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define sklgt2__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define sklgt2__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define sklgt2__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define sklgt2__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define sklgt2__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define sklgt2__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define sklgt2__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define sklgt2__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define sklgt2__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define sklgt2__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define sklgt2__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define sklgt2__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define sklgt2__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define sklgt2__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define sklgt2__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define sklgt2__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define sklgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define sklgt2__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define sklgt2__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define sklgt2__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define sklgt2__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define sklgt2__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define sklgt2__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define sklgt2__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define sklgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define sklgt2__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define sklgt2__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define sklgt2__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define sklgt2__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define sklgt2__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define sklgt2__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define sklgt2__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define sklgt2__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define sklgt2__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define sklgt2__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define sklgt2__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define sklgt2__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define sklgt2__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define sklgt2__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define sklgt2__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define sklgt2__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define sklgt2__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define sklgt2__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define sklgt2__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define sklgt2__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define sklgt2__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define sklgt2__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define sklgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define sklgt2__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define sklgt2__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define sklgt2__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define sklgt2__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define sklgt2__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define sklgt2__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define sklgt2__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define sklgt2__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define sklgt2__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define sklgt2__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define sklgt2__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define sklgt2__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define sklgt2__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define sklgt2__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define sklgt2__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define sklgt2__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define sklgt2__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define sklgt2__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define sklgt2__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define sklgt2__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define sklgt2__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define sklgt2__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define sklgt2__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define sklgt2__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define sklgt2__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define sklgt2__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define sklgt2__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define sklgt2__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define sklgt2__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define sklgt2__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define sklgt2__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define sklgt2__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define sklgt2__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define sklgt2__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define sklgt2__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define sklgt2__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define sklgt2__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define sklgt2__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define sklgt2__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define sklgt2__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define sklgt2__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define sklgt2__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define sklgt2__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define sklgt2__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define sklgt2__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define sklgt2__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ static float sklgt2__compute_extra__fpu1_active_adjusted__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 8 READ C 7 READ C 6 READ FADD C 5 READ FADD 8 FMUL FADD 100 FMUL $EuCoresTotalCount FDIV $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 8]; uint64_t tmp1 = accumulator[query->c_offset + 7]; uint64_t tmp2 = accumulator[query->c_offset + 6]; double tmp3 = tmp1 + tmp2; uint64_t tmp4 = accumulator[query->c_offset + 5]; double tmp5 = tmp3 + tmp4; double tmp6 = tmp5 * 8; double tmp7 = tmp0 + tmp6; double tmp8 = tmp7 * 100; double tmp9 = tmp8; double tmp10 = perf->sys_vars.n_eus; double tmp11 = tmp10 ? tmp9 / tmp10 : 0; double tmp12 = tmp11; double tmp13 = sklgt2__compute_extra__gpu_core_clocks__read(perf, query, accumulator); double tmp14 = tmp13 ? tmp12 / tmp13 : 0; return tmp14; } /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define sklgt2__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define sklgt2__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define sklgt2__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define sklgt2__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define sklgt2__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define sklgt2__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define sklgt2__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define sklgt2__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define sklgt2__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define sklgt2__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define sklgt2__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define sklgt2__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define sklgt2__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__sf_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define sklgt2__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define sklgt2__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define sklgt2__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define sklgt2__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define sklgt2__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define sklgt2__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define sklgt2__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define sklgt2__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define sklgt2__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define sklgt2__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define sklgt2__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define sklgt2__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define sklgt2__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define sklgt2__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define sklgt2__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define sklgt2__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define sklgt2__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define sklgt2__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define sklgt2__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define sklgt2__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define sklgt2__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define sklgt2__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ static float sklgt2__pma__stall__stc_pma_stall__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; double tmp2 = tmp0 + tmp1; double tmp3 = tmp2; double tmp4 = 2; double tmp5 = tmp4 ? tmp3 / tmp4 : 0; uint64_t tmp6 = tmp5 * 100; double tmp7 = tmp6; double tmp8 = sklgt2__pma__stall__gpu_core_clocks__read(perf, query, accumulator); double tmp9 = tmp8 ? tmp7 / tmp8 : 0; return tmp9; } /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define sklgt2__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define sklgt2__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define sklgt3__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define sklgt3__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define sklgt3__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define sklgt3__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define sklgt3__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define sklgt3__render_basic__sampler_l1_misses__read \ bdw__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define sklgt3__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define sklgt3__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define sklgt3__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define sklgt3__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define sklgt3__render_basic__l3_sampler_throughput__read \ bdw__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define sklgt3__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define sklgt3__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define sklgt3__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define sklgt3__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define sklgt3__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define sklgt3__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define sklgt3__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define sklgt3__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define sklgt3__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define sklgt3__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define sklgt3__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define sklgt3__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define sklgt3__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt3__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt3__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define sklgt3__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define sklgt3__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define sklgt3__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define sklgt3__render_basic__l3_lookups__read \ bdw__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define sklgt3__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define sklgt3__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define sklgt3__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define sklgt3__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define sklgt3__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define sklgt3__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define sklgt3__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define sklgt3__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define sklgt3__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define sklgt3__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define sklgt3__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define sklgt3__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define sklgt3__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define sklgt3__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define sklgt3__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define sklgt3__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define sklgt3__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define sklgt3__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define sklgt3__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define sklgt3__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define sklgt3__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define sklgt3__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define sklgt3__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define sklgt3__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define sklgt3__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define sklgt3__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define sklgt3__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define sklgt3__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define sklgt3__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define sklgt3__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define sklgt3__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define sklgt3__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define sklgt3__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define sklgt3__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define sklgt3__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define sklgt3__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define sklgt3__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define sklgt3__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define sklgt3__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define sklgt3__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define sklgt3__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define sklgt3__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define sklgt3__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define sklgt3__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define sklgt3__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define sklgt3__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define sklgt3__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define sklgt3__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define sklgt3__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define sklgt3__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define sklgt3__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define sklgt3__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define sklgt3__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define sklgt3__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define sklgt3__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define sklgt3__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define sklgt3__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define sklgt3__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define sklgt3__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define sklgt3__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define sklgt3__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define sklgt3__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define sklgt3__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define sklgt3__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define sklgt3__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define sklgt3__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define sklgt3__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define sklgt3__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define sklgt3__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define sklgt3__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define sklgt3__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define sklgt3__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define sklgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define sklgt3__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define sklgt3__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define sklgt3__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define sklgt3__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define sklgt3__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define sklgt3__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define sklgt3__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define sklgt3__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define sklgt3__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define sklgt3__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define sklgt3__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define sklgt3__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define sklgt3__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define sklgt3__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define sklgt3__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define sklgt3__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define sklgt3__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define sklgt3__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define sklgt3__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define sklgt3__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define sklgt3__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define sklgt3__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define sklgt3__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define sklgt3__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define sklgt3__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define sklgt3__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define sklgt3__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define sklgt3__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define sklgt3__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define sklgt3__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define sklgt3__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define sklgt3__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define sklgt3__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define sklgt3__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define sklgt3__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define sklgt3__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define sklgt3__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define sklgt3__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define sklgt3__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define sklgt3__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define sklgt3__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define sklgt3__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define sklgt3__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define sklgt3__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt3__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt3__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define sklgt3__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define sklgt3__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define sklgt3__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define sklgt3__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define sklgt3__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define sklgt3__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define sklgt3__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define sklgt3__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define sklgt3__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define sklgt3__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define sklgt3__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define sklgt3__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define sklgt3__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define sklgt3__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define sklgt3__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define sklgt3__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define sklgt3__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define sklgt3__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define sklgt3__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define sklgt3__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define sklgt3__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define sklgt3__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define sklgt3__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define sklgt3__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define sklgt3__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define sklgt3__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define sklgt3__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define sklgt3__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define sklgt3__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define sklgt3__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define sklgt3__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define sklgt3__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define sklgt3__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define sklgt3__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define sklgt3__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define sklgt3__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define sklgt3__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define sklgt3__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define sklgt3__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define sklgt3__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define sklgt3__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define sklgt3__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define sklgt3__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt3__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt3__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define sklgt3__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define sklgt3__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define sklgt3__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define sklgt3__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define sklgt3__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define sklgt3__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define sklgt3__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define sklgt3__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define sklgt3__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define sklgt3__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define sklgt3__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define sklgt3__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define sklgt3__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define sklgt3__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define sklgt3__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define sklgt3__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define sklgt3__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define sklgt3__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define sklgt3__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define sklgt3__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define sklgt3__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define sklgt3__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define sklgt3__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define sklgt3__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define sklgt3__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define sklgt3__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define sklgt3__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define sklgt3__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define sklgt3__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define sklgt3__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define sklgt3__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define sklgt3__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define sklgt3__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define sklgt3__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define sklgt3__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define sklgt3__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define sklgt3__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define sklgt3__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define sklgt3__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define sklgt3__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define sklgt3__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define sklgt3__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define sklgt3__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define sklgt3__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define sklgt3__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define sklgt3__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define sklgt3__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define sklgt3__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define sklgt3__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define sklgt3__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define sklgt3__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define sklgt3__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define sklgt3__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define sklgt3__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define sklgt3__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define sklgt3__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define sklgt3__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define sklgt3__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define sklgt3__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define sklgt3__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define sklgt3__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define sklgt3__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define sklgt3__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define sklgt3__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define sklgt3__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define sklgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define sklgt3__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define sklgt3__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define sklgt3__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define sklgt3__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define sklgt3__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define sklgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define sklgt3__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define sklgt3__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define sklgt3__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define sklgt3__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define sklgt3__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define sklgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define sklgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define sklgt3__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define sklgt3__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define sklgt3__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define sklgt3__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define sklgt3__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define sklgt3__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define sklgt3__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define sklgt3__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define sklgt3__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define sklgt3__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define sklgt3__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define sklgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define sklgt3__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define sklgt3__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define sklgt3__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define sklgt3__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define sklgt3__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define sklgt3__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define sklgt3__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define sklgt3__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define sklgt3__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define sklgt3__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define sklgt3__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define sklgt3__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define sklgt3__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define sklgt3__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define sklgt3__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define sklgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define sklgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define sklgt3__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define sklgt3__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define sklgt3__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define sklgt3__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define sklgt3__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define sklgt3__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define sklgt3__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define sklgt3__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define sklgt3__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define sklgt3__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define sklgt3__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define sklgt3__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define sklgt3__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define sklgt3__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define sklgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define sklgt3__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define sklgt3__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define sklgt3__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define sklgt3__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define sklgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define sklgt3__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define sklgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define sklgt3__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define sklgt3__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define sklgt3__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define sklgt3__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define sklgt3__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define sklgt3__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define sklgt3__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define sklgt3__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define sklgt3__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define sklgt3__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define sklgt3__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define sklgt3__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define sklgt3__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define sklgt3__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define sklgt3__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define sklgt3__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define sklgt3__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define sklgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define sklgt3__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define sklgt3__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define sklgt3__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define sklgt3__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define sklgt3__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define sklgt3__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define sklgt3__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define sklgt3__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define sklgt3__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define sklgt3__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define sklgt3__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define sklgt3__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define sklgt3__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define sklgt3__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define sklgt3__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define sklgt3__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define sklgt3__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define sklgt3__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define sklgt3__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define sklgt3__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define sklgt3__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define sklgt3__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define sklgt3__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define sklgt3__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define sklgt3__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define sklgt3__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define sklgt3__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define sklgt3__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define sklgt3__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define sklgt3__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define sklgt3__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define sklgt3__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define sklgt3__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define sklgt3__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define sklgt3__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define sklgt3__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define sklgt3__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define sklgt3__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define sklgt3__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define sklgt3__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define sklgt3__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define sklgt3__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define sklgt3__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define sklgt3__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define sklgt3__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define sklgt3__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define sklgt3__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define sklgt3__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define sklgt3__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define sklgt3__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define sklgt3__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define sklgt3__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define sklgt3__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define sklgt3__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define sklgt3__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define sklgt3__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define sklgt3__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define sklgt3__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define sklgt3__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define sklgt3__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define sklgt3__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define sklgt3__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define sklgt3__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define sklgt3__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define sklgt3__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define sklgt3__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define sklgt3__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define sklgt3__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define sklgt3__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define sklgt3__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define sklgt3__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define sklgt3__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define sklgt3__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define sklgt3__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define sklgt3__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define sklgt3__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define sklgt3__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define sklgt3__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define sklgt3__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define sklgt3__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define sklgt3__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define sklgt3__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define sklgt3__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define sklgt3__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define sklgt3__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define sklgt3__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define sklgt3__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define sklgt3__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define sklgt3__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define sklgt3__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define sklgt3__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define sklgt3__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define sklgt3__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define sklgt3__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define sklgt3__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define sklgt3__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define sklgt3__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define sklgt3__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define sklgt3__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define sklgt3__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define sklgt3__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define sklgt3__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define sklgt3__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define sklgt3__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define sklgt3__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define sklgt3__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define sklgt3__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define sklgt3__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define sklgt3__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define sklgt3__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define sklgt3__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define sklgt3__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define sklgt3__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define sklgt3__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define sklgt3__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define sklgt3__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define sklgt3__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define sklgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define sklgt3__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define sklgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define sklgt3__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define sklgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define sklgt3__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define sklgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define sklgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define sklgt3__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define sklgt3__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define sklgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define sklgt3__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define sklgt3__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define sklgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define sklgt3__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define sklgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define sklgt3__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define sklgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define sklgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define sklgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define sklgt3__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define sklgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define sklgt3__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define sklgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define sklgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define sklgt3__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define sklgt3__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define sklgt3__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define sklgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define sklgt3__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define sklgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define sklgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define sklgt3__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define sklgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define sklgt3__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define sklgt3__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define sklgt3__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define sklgt3__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define sklgt3__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define sklgt3__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define sklgt3__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define sklgt3__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define sklgt3__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define sklgt3__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define sklgt3__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define sklgt3__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define sklgt3__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define sklgt3__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define sklgt3__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define sklgt3__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define sklgt3__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define sklgt3__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define sklgt3__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define sklgt3__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define sklgt3__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define sklgt3__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define sklgt3__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define sklgt3__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define sklgt3__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define sklgt3__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define sklgt3__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define sklgt3__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define sklgt3__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define sklgt3__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define sklgt3__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define sklgt3__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define sklgt3__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define sklgt3__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define sklgt3__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define sklgt3__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define sklgt3__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define sklgt3__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define sklgt3__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define sklgt3__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define sklgt3__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define sklgt3__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define sklgt3__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define sklgt3__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define sklgt3__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define sklgt3__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define sklgt3__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define sklgt3__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define sklgt3__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define sklgt3__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define sklgt3__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define sklgt3__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define sklgt3__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define sklgt3__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define sklgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define sklgt3__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define sklgt3__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define sklgt3__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define sklgt3__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define sklgt3__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define sklgt3__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define sklgt3__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define sklgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define sklgt3__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define sklgt3__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define sklgt3__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define sklgt3__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define sklgt3__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define sklgt3__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define sklgt3__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define sklgt3__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define sklgt3__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define sklgt3__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define sklgt3__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define sklgt3__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define sklgt3__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define sklgt3__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define sklgt3__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define sklgt3__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define sklgt3__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define sklgt3__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define sklgt3__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define sklgt3__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define sklgt3__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define sklgt3__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define sklgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define sklgt3__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define sklgt3__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define sklgt3__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define sklgt3__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define sklgt3__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define sklgt3__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define sklgt3__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define sklgt3__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define sklgt3__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define sklgt3__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define sklgt3__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define sklgt3__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define sklgt3__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define sklgt3__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define sklgt3__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define sklgt3__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define sklgt3__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define sklgt3__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define sklgt3__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define sklgt3__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define sklgt3__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define sklgt3__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define sklgt3__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define sklgt3__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define sklgt3__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define sklgt3__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define sklgt3__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define sklgt3__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define sklgt3__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define sklgt3__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define sklgt3__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define sklgt3__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define sklgt3__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define sklgt3__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define sklgt3__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define sklgt3__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define sklgt3__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define sklgt3__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define sklgt3__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define sklgt3__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define sklgt3__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define sklgt3__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define sklgt3__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define sklgt3__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define sklgt3__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define sklgt3__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define sklgt3__compute_extra__fpu1_active_adjusted__read \ bdw__compute_extra__fpu1_active_adjusted__read /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define sklgt3__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define sklgt3__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define sklgt3__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define sklgt3__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define sklgt3__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define sklgt3__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define sklgt3__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define sklgt3__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define sklgt3__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define sklgt3__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define sklgt3__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define sklgt3__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define sklgt3__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define sklgt3__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define sklgt3__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define sklgt3__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define sklgt3__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define sklgt3__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define sklgt3__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__so_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define sklgt3__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* Gpu Rings Busyness :: Vdbox1 Ring Busy */ #define sklgt3__gpu_busyness__vdbox1_busy__read \ bdw__render_pipe_profile__sf_stall__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define sklgt3__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define sklgt3__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define sklgt3__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define sklgt3__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define sklgt3__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define sklgt3__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define sklgt3__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define sklgt3__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define sklgt3__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define sklgt3__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define sklgt3__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define sklgt3__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define sklgt3__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define sklgt3__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define sklgt3__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define sklgt3__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define sklgt3__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define sklgt3__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define sklgt4__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define sklgt4__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define sklgt4__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define sklgt4__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define sklgt4__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ static uint64_t sklgt4__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ UADD B 3 READ UADD 8 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->b_offset + 3]; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = tmp4 * 8; return tmp5; } /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define sklgt4__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define sklgt4__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define sklgt4__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ static uint64_t sklgt4__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses 64 UMUL */ uint64_t tmp0 = sklgt4__render_basic__sampler_l1_misses__read(perf, query, accumulator) * 64; return tmp0; } /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define sklgt4__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define sklgt4__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define sklgt4__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define sklgt4__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define sklgt4__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define sklgt4__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define sklgt4__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define sklgt4__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define sklgt4__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define sklgt4__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define sklgt4__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define sklgt4__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define sklgt4__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt4__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt4__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define sklgt4__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define sklgt4__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define sklgt4__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ static uint64_t sklgt4__render_basic__l3_lookups__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ uint64_t tmp0 = sklgt4__render_basic__sampler_l1_misses__read(perf, query, accumulator) + sklgt4__render_basic__shader_memory_accesses__read(perf, query, accumulator); return tmp0; } /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define sklgt4__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define sklgt4__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define sklgt4__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define sklgt4__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define sklgt4__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define sklgt4__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define sklgt4__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define sklgt4__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define sklgt4__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define sklgt4__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define sklgt4__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define sklgt4__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define sklgt4__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define sklgt4__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define sklgt4__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define sklgt4__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define sklgt4__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define sklgt4__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define sklgt4__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define sklgt4__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define sklgt4__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define sklgt4__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define sklgt4__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define sklgt4__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define sklgt4__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define sklgt4__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define sklgt4__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define sklgt4__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define sklgt4__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define sklgt4__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define sklgt4__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define sklgt4__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define sklgt4__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define sklgt4__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define sklgt4__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define sklgt4__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define sklgt4__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define sklgt4__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define sklgt4__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define sklgt4__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define sklgt4__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define sklgt4__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define sklgt4__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define sklgt4__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define sklgt4__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define sklgt4__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define sklgt4__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define sklgt4__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define sklgt4__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define sklgt4__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define sklgt4__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define sklgt4__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define sklgt4__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define sklgt4__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define sklgt4__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define sklgt4__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define sklgt4__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define sklgt4__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define sklgt4__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define sklgt4__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define sklgt4__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define sklgt4__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define sklgt4__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define sklgt4__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define sklgt4__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define sklgt4__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define sklgt4__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define sklgt4__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define sklgt4__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define sklgt4__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define sklgt4__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define sklgt4__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define sklgt4__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define sklgt4__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define sklgt4__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define sklgt4__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define sklgt4__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define sklgt4__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define sklgt4__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define sklgt4__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define sklgt4__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define sklgt4__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define sklgt4__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define sklgt4__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define sklgt4__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define sklgt4__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define sklgt4__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define sklgt4__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define sklgt4__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define sklgt4__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define sklgt4__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define sklgt4__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define sklgt4__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define sklgt4__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define sklgt4__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define sklgt4__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define sklgt4__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define sklgt4__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define sklgt4__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define sklgt4__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define sklgt4__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define sklgt4__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define sklgt4__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define sklgt4__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define sklgt4__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define sklgt4__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define sklgt4__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define sklgt4__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define sklgt4__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define sklgt4__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define sklgt4__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define sklgt4__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define sklgt4__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define sklgt4__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define sklgt4__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define sklgt4__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define sklgt4__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt4__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt4__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define sklgt4__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define sklgt4__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define sklgt4__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define sklgt4__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define sklgt4__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define sklgt4__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define sklgt4__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define sklgt4__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define sklgt4__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define sklgt4__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define sklgt4__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define sklgt4__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define sklgt4__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define sklgt4__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define sklgt4__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define sklgt4__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define sklgt4__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define sklgt4__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define sklgt4__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define sklgt4__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define sklgt4__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define sklgt4__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define sklgt4__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define sklgt4__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define sklgt4__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define sklgt4__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define sklgt4__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define sklgt4__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define sklgt4__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define sklgt4__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define sklgt4__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define sklgt4__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define sklgt4__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define sklgt4__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define sklgt4__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define sklgt4__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define sklgt4__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define sklgt4__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define sklgt4__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define sklgt4__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define sklgt4__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define sklgt4__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define sklgt4__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt4__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define sklgt4__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define sklgt4__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define sklgt4__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define sklgt4__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define sklgt4__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define sklgt4__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define sklgt4__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define sklgt4__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define sklgt4__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define sklgt4__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define sklgt4__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define sklgt4__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define sklgt4__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define sklgt4__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define sklgt4__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define sklgt4__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define sklgt4__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define sklgt4__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define sklgt4__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define sklgt4__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define sklgt4__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define sklgt4__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define sklgt4__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define sklgt4__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define sklgt4__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define sklgt4__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define sklgt4__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define sklgt4__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define sklgt4__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define sklgt4__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define sklgt4__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define sklgt4__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define sklgt4__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define sklgt4__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define sklgt4__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define sklgt4__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define sklgt4__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define sklgt4__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define sklgt4__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define sklgt4__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define sklgt4__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define sklgt4__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define sklgt4__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define sklgt4__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define sklgt4__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define sklgt4__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define sklgt4__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define sklgt4__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define sklgt4__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define sklgt4__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define sklgt4__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define sklgt4__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define sklgt4__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define sklgt4__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define sklgt4__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define sklgt4__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define sklgt4__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define sklgt4__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define sklgt4__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define sklgt4__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define sklgt4__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define sklgt4__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define sklgt4__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define sklgt4__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define sklgt4__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define sklgt4__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define sklgt4__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define sklgt4__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define sklgt4__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define sklgt4__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define sklgt4__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define sklgt4__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define sklgt4__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define sklgt4__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define sklgt4__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define sklgt4__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define sklgt4__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define sklgt4__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define sklgt4__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define sklgt4__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define sklgt4__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define sklgt4__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define sklgt4__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define sklgt4__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define sklgt4__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define sklgt4__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define sklgt4__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define sklgt4__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define sklgt4__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define sklgt4__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define sklgt4__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define sklgt4__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define sklgt4__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define sklgt4__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define sklgt4__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define sklgt4__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define sklgt4__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define sklgt4__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define sklgt4__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define sklgt4__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define sklgt4__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define sklgt4__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define sklgt4__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define sklgt4__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define sklgt4__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define sklgt4__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define sklgt4__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define sklgt4__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define sklgt4__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define sklgt4__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define sklgt4__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define sklgt4__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define sklgt4__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define sklgt4__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define sklgt4__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define sklgt4__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define sklgt4__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define sklgt4__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define sklgt4__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define sklgt4__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define sklgt4__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define sklgt4__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define sklgt4__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define sklgt4__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define sklgt4__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define sklgt4__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define sklgt4__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define sklgt4__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define sklgt4__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define sklgt4__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define sklgt4__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define sklgt4__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define sklgt4__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define sklgt4__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define sklgt4__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define sklgt4__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define sklgt4__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define sklgt4__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define sklgt4__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define sklgt4__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define sklgt4__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define sklgt4__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define sklgt4__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define sklgt4__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define sklgt4__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define sklgt4__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define sklgt4__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define sklgt4__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define sklgt4__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define sklgt4__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define sklgt4__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define sklgt4__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define sklgt4__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define sklgt4__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define sklgt4__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define sklgt4__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define sklgt4__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define sklgt4__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define sklgt4__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define sklgt4__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define sklgt4__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define sklgt4__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define sklgt4__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define sklgt4__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define sklgt4__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define sklgt4__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define sklgt4__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define sklgt4__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define sklgt4__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define sklgt4__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define sklgt4__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define sklgt4__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define sklgt4__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define sklgt4__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define sklgt4__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define sklgt4__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define sklgt4__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define sklgt4__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define sklgt4__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define sklgt4__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define sklgt4__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define sklgt4__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define sklgt4__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define sklgt4__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define sklgt4__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define sklgt4__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define sklgt4__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define sklgt4__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define sklgt4__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define sklgt4__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define sklgt4__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define sklgt4__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define sklgt4__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define sklgt4__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define sklgt4__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define sklgt4__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define sklgt4__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define sklgt4__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define sklgt4__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define sklgt4__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define sklgt4__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define sklgt4__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define sklgt4__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define sklgt4__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define sklgt4__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define sklgt4__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define sklgt4__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define sklgt4__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define sklgt4__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define sklgt4__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define sklgt4__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define sklgt4__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define sklgt4__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define sklgt4__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define sklgt4__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define sklgt4__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define sklgt4__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define sklgt4__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define sklgt4__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define sklgt4__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define sklgt4__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define sklgt4__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define sklgt4__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define sklgt4__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define sklgt4__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define sklgt4__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define sklgt4__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define sklgt4__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define sklgt4__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define sklgt4__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define sklgt4__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define sklgt4__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define sklgt4__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define sklgt4__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define sklgt4__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define sklgt4__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define sklgt4__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define sklgt4__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define sklgt4__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define sklgt4__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define sklgt4__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define sklgt4__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define sklgt4__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define sklgt4__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define sklgt4__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define sklgt4__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define sklgt4__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define sklgt4__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define sklgt4__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define sklgt4__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define sklgt4__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define sklgt4__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define sklgt4__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define sklgt4__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define sklgt4__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define sklgt4__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define sklgt4__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define sklgt4__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define sklgt4__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define sklgt4__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define sklgt4__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define sklgt4__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define sklgt4__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define sklgt4__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define sklgt4__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define sklgt4__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define sklgt4__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define sklgt4__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define sklgt4__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define sklgt4__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define sklgt4__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define sklgt4__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define sklgt4__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define sklgt4__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define sklgt4__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define sklgt4__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define sklgt4__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define sklgt4__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define sklgt4__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define sklgt4__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define sklgt4__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define sklgt4__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define sklgt4__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define sklgt4__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define sklgt4__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define sklgt4__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define sklgt4__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define sklgt4__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define sklgt4__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define sklgt4__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define sklgt4__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define sklgt4__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define sklgt4__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define sklgt4__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define sklgt4__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define sklgt4__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define sklgt4__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define sklgt4__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define sklgt4__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define sklgt4__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define sklgt4__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define sklgt4__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define sklgt4__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define sklgt4__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define sklgt4__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define sklgt4__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define sklgt4__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define sklgt4__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define sklgt4__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define sklgt4__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define sklgt4__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define sklgt4__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define sklgt4__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define sklgt4__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define sklgt4__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define sklgt4__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define sklgt4__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define sklgt4__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define sklgt4__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define sklgt4__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define sklgt4__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define sklgt4__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define sklgt4__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define sklgt4__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define sklgt4__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define sklgt4__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define sklgt4__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define sklgt4__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define sklgt4__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define sklgt4__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define sklgt4__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define sklgt4__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define sklgt4__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define sklgt4__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define sklgt4__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define sklgt4__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define sklgt4__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define sklgt4__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define sklgt4__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define sklgt4__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define sklgt4__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define sklgt4__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define sklgt4__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define sklgt4__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define sklgt4__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define sklgt4__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define sklgt4__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define sklgt4__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define sklgt4__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define sklgt4__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define sklgt4__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define sklgt4__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define sklgt4__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define sklgt4__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define sklgt4__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define sklgt4__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define sklgt4__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define sklgt4__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define sklgt4__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define sklgt4__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define sklgt4__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define sklgt4__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define sklgt4__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define sklgt4__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define sklgt4__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define sklgt4__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define sklgt4__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define sklgt4__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define sklgt4__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define sklgt4__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define sklgt4__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define sklgt4__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define sklgt4__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define sklgt4__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define sklgt4__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define sklgt4__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define sklgt4__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define sklgt4__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define sklgt4__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define sklgt4__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define sklgt4__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define sklgt4__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define sklgt4__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define sklgt4__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define sklgt4__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define sklgt4__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define sklgt4__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define sklgt4__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define sklgt4__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define sklgt4__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define sklgt4__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define sklgt4__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define sklgt4__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define sklgt4__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define sklgt4__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define sklgt4__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define sklgt4__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define sklgt4__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define sklgt4__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define sklgt4__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define sklgt4__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define sklgt4__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define sklgt4__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define sklgt4__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define sklgt4__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define sklgt4__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define sklgt4__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define sklgt4__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define sklgt4__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define sklgt4__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define sklgt4__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define sklgt4__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define sklgt4__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define sklgt4__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define sklgt4__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define sklgt4__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define sklgt4__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define sklgt4__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define sklgt4__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define sklgt4__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define sklgt4__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define sklgt4__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define sklgt4__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define sklgt4__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define sklgt4__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define sklgt4__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define sklgt4__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define sklgt4__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define sklgt4__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define sklgt4__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define sklgt4__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define sklgt4__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define sklgt4__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define sklgt4__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define sklgt4__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define sklgt4__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define sklgt4__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define sklgt4__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define sklgt4__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define sklgt4__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define sklgt4__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define sklgt4__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define sklgt4__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define sklgt4__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define sklgt4__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define sklgt4__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define sklgt4__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define sklgt4__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define sklgt4__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define sklgt4__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define sklgt4__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__so_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define sklgt4__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* Gpu Rings Busyness :: Vdbox1 Ring Busy */ #define sklgt4__gpu_busyness__vdbox1_busy__read \ bdw__render_pipe_profile__sf_stall__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define sklgt4__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define sklgt4__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define sklgt4__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define sklgt4__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define sklgt4__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define sklgt4__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define sklgt4__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define sklgt4__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define sklgt4__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define sklgt4__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define sklgt4__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define sklgt4__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define sklgt4__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define sklgt4__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define sklgt4__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define sklgt4__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define sklgt4__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define sklgt4__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define kblgt2__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define kblgt2__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define kblgt2__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define kblgt2__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define kblgt2__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define kblgt2__render_basic__sampler_l1_misses__read \ sklgt2__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define kblgt2__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define kblgt2__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define kblgt2__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define kblgt2__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define kblgt2__render_basic__l3_sampler_throughput__read \ sklgt2__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define kblgt2__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define kblgt2__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define kblgt2__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define kblgt2__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define kblgt2__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define kblgt2__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define kblgt2__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define kblgt2__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define kblgt2__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define kblgt2__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define kblgt2__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define kblgt2__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define kblgt2__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt2__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt2__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define kblgt2__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define kblgt2__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define kblgt2__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define kblgt2__render_basic__l3_lookups__read \ sklgt2__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define kblgt2__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define kblgt2__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define kblgt2__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define kblgt2__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define kblgt2__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define kblgt2__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define kblgt2__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define kblgt2__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define kblgt2__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define kblgt2__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define kblgt2__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define kblgt2__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define kblgt2__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define kblgt2__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define kblgt2__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define kblgt2__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define kblgt2__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define kblgt2__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define kblgt2__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define kblgt2__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define kblgt2__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define kblgt2__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define kblgt2__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define kblgt2__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define kblgt2__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define kblgt2__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define kblgt2__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define kblgt2__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define kblgt2__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define kblgt2__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define kblgt2__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define kblgt2__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define kblgt2__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define kblgt2__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define kblgt2__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define kblgt2__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define kblgt2__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define kblgt2__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define kblgt2__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define kblgt2__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define kblgt2__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define kblgt2__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define kblgt2__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define kblgt2__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define kblgt2__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define kblgt2__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define kblgt2__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define kblgt2__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define kblgt2__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define kblgt2__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define kblgt2__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define kblgt2__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define kblgt2__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define kblgt2__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define kblgt2__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define kblgt2__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define kblgt2__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define kblgt2__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define kblgt2__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define kblgt2__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define kblgt2__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define kblgt2__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define kblgt2__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define kblgt2__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define kblgt2__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define kblgt2__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define kblgt2__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define kblgt2__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define kblgt2__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define kblgt2__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define kblgt2__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define kblgt2__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define kblgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define kblgt2__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define kblgt2__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define kblgt2__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define kblgt2__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define kblgt2__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define kblgt2__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define kblgt2__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define kblgt2__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define kblgt2__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define kblgt2__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define kblgt2__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define kblgt2__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define kblgt2__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define kblgt2__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define kblgt2__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define kblgt2__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define kblgt2__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define kblgt2__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define kblgt2__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define kblgt2__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define kblgt2__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define kblgt2__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define kblgt2__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define kblgt2__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define kblgt2__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define kblgt2__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define kblgt2__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define kblgt2__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define kblgt2__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define kblgt2__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define kblgt2__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define kblgt2__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define kblgt2__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define kblgt2__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define kblgt2__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define kblgt2__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define kblgt2__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define kblgt2__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define kblgt2__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define kblgt2__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define kblgt2__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define kblgt2__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define kblgt2__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define kblgt2__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt2__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt2__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define kblgt2__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define kblgt2__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define kblgt2__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define kblgt2__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define kblgt2__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define kblgt2__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define kblgt2__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define kblgt2__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define kblgt2__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define kblgt2__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define kblgt2__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define kblgt2__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define kblgt2__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define kblgt2__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define kblgt2__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define kblgt2__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define kblgt2__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define kblgt2__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define kblgt2__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define kblgt2__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define kblgt2__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define kblgt2__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define kblgt2__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define kblgt2__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define kblgt2__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define kblgt2__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define kblgt2__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define kblgt2__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define kblgt2__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define kblgt2__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define kblgt2__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define kblgt2__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define kblgt2__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define kblgt2__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define kblgt2__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define kblgt2__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define kblgt2__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define kblgt2__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define kblgt2__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define kblgt2__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define kblgt2__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define kblgt2__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define kblgt2__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt2__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt2__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define kblgt2__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define kblgt2__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define kblgt2__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define kblgt2__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define kblgt2__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define kblgt2__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define kblgt2__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define kblgt2__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define kblgt2__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define kblgt2__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define kblgt2__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define kblgt2__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define kblgt2__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define kblgt2__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define kblgt2__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define kblgt2__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define kblgt2__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define kblgt2__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define kblgt2__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define kblgt2__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define kblgt2__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define kblgt2__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define kblgt2__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define kblgt2__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define kblgt2__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define kblgt2__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define kblgt2__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define kblgt2__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define kblgt2__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define kblgt2__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define kblgt2__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define kblgt2__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define kblgt2__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define kblgt2__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define kblgt2__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define kblgt2__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define kblgt2__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define kblgt2__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define kblgt2__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define kblgt2__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define kblgt2__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define kblgt2__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define kblgt2__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define kblgt2__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define kblgt2__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define kblgt2__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define kblgt2__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define kblgt2__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define kblgt2__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define kblgt2__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define kblgt2__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define kblgt2__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define kblgt2__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define kblgt2__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define kblgt2__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define kblgt2__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define kblgt2__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define kblgt2__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define kblgt2__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define kblgt2__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define kblgt2__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define kblgt2__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define kblgt2__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define kblgt2__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define kblgt2__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define kblgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define kblgt2__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define kblgt2__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define kblgt2__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define kblgt2__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define kblgt2__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define kblgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define kblgt2__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define kblgt2__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define kblgt2__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define kblgt2__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define kblgt2__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define kblgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define kblgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define kblgt2__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define kblgt2__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define kblgt2__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define kblgt2__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define kblgt2__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define kblgt2__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define kblgt2__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define kblgt2__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define kblgt2__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define kblgt2__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define kblgt2__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define kblgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define kblgt2__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define kblgt2__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define kblgt2__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define kblgt2__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define kblgt2__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define kblgt2__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define kblgt2__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define kblgt2__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define kblgt2__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define kblgt2__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define kblgt2__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define kblgt2__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define kblgt2__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define kblgt2__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define kblgt2__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define kblgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define kblgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define kblgt2__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define kblgt2__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define kblgt2__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define kblgt2__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define kblgt2__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define kblgt2__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define kblgt2__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define kblgt2__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define kblgt2__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define kblgt2__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define kblgt2__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define kblgt2__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define kblgt2__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define kblgt2__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define kblgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define kblgt2__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define kblgt2__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define kblgt2__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define kblgt2__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define kblgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define kblgt2__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define kblgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define kblgt2__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define kblgt2__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define kblgt2__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define kblgt2__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define kblgt2__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define kblgt2__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define kblgt2__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define kblgt2__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define kblgt2__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define kblgt2__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define kblgt2__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define kblgt2__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define kblgt2__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define kblgt2__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define kblgt2__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define kblgt2__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define kblgt2__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define kblgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define kblgt2__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define kblgt2__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define kblgt2__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define kblgt2__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define kblgt2__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define kblgt2__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define kblgt2__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define kblgt2__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define kblgt2__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define kblgt2__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define kblgt2__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define kblgt2__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define kblgt2__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define kblgt2__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define kblgt2__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define kblgt2__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define kblgt2__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define kblgt2__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define kblgt2__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define kblgt2__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define kblgt2__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define kblgt2__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define kblgt2__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define kblgt2__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define kblgt2__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define kblgt2__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define kblgt2__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define kblgt2__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define kblgt2__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define kblgt2__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define kblgt2__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define kblgt2__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define kblgt2__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define kblgt2__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define kblgt2__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define kblgt2__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define kblgt2__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define kblgt2__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define kblgt2__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define kblgt2__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define kblgt2__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define kblgt2__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define kblgt2__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define kblgt2__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define kblgt2__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define kblgt2__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define kblgt2__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define kblgt2__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define kblgt2__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define kblgt2__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define kblgt2__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define kblgt2__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define kblgt2__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define kblgt2__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define kblgt2__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define kblgt2__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define kblgt2__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define kblgt2__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define kblgt2__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define kblgt2__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define kblgt2__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define kblgt2__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define kblgt2__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define kblgt2__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define kblgt2__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define kblgt2__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define kblgt2__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define kblgt2__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define kblgt2__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define kblgt2__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define kblgt2__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define kblgt2__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define kblgt2__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define kblgt2__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define kblgt2__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define kblgt2__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define kblgt2__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define kblgt2__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define kblgt2__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define kblgt2__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define kblgt2__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define kblgt2__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define kblgt2__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define kblgt2__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define kblgt2__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define kblgt2__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define kblgt2__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define kblgt2__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define kblgt2__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define kblgt2__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define kblgt2__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define kblgt2__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define kblgt2__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define kblgt2__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define kblgt2__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define kblgt2__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define kblgt2__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define kblgt2__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define kblgt2__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define kblgt2__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define kblgt2__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define kblgt2__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define kblgt2__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define kblgt2__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define kblgt2__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define kblgt2__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define kblgt2__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define kblgt2__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define kblgt2__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define kblgt2__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define kblgt2__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define kblgt2__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define kblgt2__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define kblgt2__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define kblgt2__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define kblgt2__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define kblgt2__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define kblgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define kblgt2__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define kblgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define kblgt2__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define kblgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define kblgt2__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define kblgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define kblgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define kblgt2__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define kblgt2__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define kblgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define kblgt2__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define kblgt2__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define kblgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define kblgt2__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define kblgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define kblgt2__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define kblgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define kblgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define kblgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define kblgt2__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define kblgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define kblgt2__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define kblgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define kblgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define kblgt2__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define kblgt2__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define kblgt2__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define kblgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define kblgt2__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define kblgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define kblgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define kblgt2__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define kblgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define kblgt2__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define kblgt2__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define kblgt2__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define kblgt2__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define kblgt2__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define kblgt2__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define kblgt2__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define kblgt2__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define kblgt2__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define kblgt2__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define kblgt2__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define kblgt2__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define kblgt2__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define kblgt2__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define kblgt2__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define kblgt2__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define kblgt2__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define kblgt2__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define kblgt2__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define kblgt2__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define kblgt2__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define kblgt2__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define kblgt2__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define kblgt2__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define kblgt2__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define kblgt2__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define kblgt2__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define kblgt2__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define kblgt2__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define kblgt2__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define kblgt2__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define kblgt2__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define kblgt2__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define kblgt2__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define kblgt2__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define kblgt2__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define kblgt2__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define kblgt2__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define kblgt2__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define kblgt2__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define kblgt2__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define kblgt2__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define kblgt2__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define kblgt2__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define kblgt2__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define kblgt2__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define kblgt2__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define kblgt2__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define kblgt2__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define kblgt2__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define kblgt2__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define kblgt2__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define kblgt2__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define kblgt2__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define kblgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define kblgt2__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define kblgt2__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define kblgt2__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define kblgt2__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define kblgt2__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define kblgt2__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define kblgt2__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define kblgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define kblgt2__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define kblgt2__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define kblgt2__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define kblgt2__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define kblgt2__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define kblgt2__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define kblgt2__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define kblgt2__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define kblgt2__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define kblgt2__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define kblgt2__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define kblgt2__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define kblgt2__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define kblgt2__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define kblgt2__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define kblgt2__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define kblgt2__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define kblgt2__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define kblgt2__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define kblgt2__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define kblgt2__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define kblgt2__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define kblgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define kblgt2__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define kblgt2__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define kblgt2__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define kblgt2__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define kblgt2__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define kblgt2__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define kblgt2__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define kblgt2__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define kblgt2__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define kblgt2__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define kblgt2__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define kblgt2__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define kblgt2__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define kblgt2__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define kblgt2__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define kblgt2__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define kblgt2__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define kblgt2__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define kblgt2__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define kblgt2__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define kblgt2__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define kblgt2__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define kblgt2__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define kblgt2__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define kblgt2__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define kblgt2__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define kblgt2__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define kblgt2__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define kblgt2__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define kblgt2__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define kblgt2__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define kblgt2__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define kblgt2__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define kblgt2__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define kblgt2__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define kblgt2__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define kblgt2__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define kblgt2__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define kblgt2__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define kblgt2__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define kblgt2__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define kblgt2__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define kblgt2__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define kblgt2__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define kblgt2__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define kblgt2__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define kblgt2__compute_extra__fpu1_active_adjusted__read \ sklgt2__compute_extra__fpu1_active_adjusted__read /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define kblgt2__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define kblgt2__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define kblgt2__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define kblgt2__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define kblgt2__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define kblgt2__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define kblgt2__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define kblgt2__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define kblgt2__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define kblgt2__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define kblgt2__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define kblgt2__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define kblgt2__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__sf_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define kblgt2__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define kblgt2__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define kblgt2__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define kblgt2__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define kblgt2__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define kblgt2__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define kblgt2__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* MDAPI testing set Gen9.5 :: TestCounter7 */ #define kblgt2__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9.5 :: GPU Time Elapsed */ #define kblgt2__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9.5 :: GPU Core Clocks */ #define kblgt2__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ #define kblgt2__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ #define kblgt2__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9.5 :: TestCounter8 */ #define kblgt2__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9.5 :: TestCounter4 */ #define kblgt2__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9.5 :: TestCounter5 */ #define kblgt2__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9.5 :: TestCounter6 */ #define kblgt2__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9.5 :: TestCounter3 */ #define kblgt2__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9.5 :: TestCounter0 */ #define kblgt2__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9.5 :: TestCounter1 */ #define kblgt2__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9.5 :: TestCounter2 */ #define kblgt2__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define kblgt2__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define kblgt2__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define kblgt2__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define kblgt2__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define kblgt2__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define kblgt3__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define kblgt3__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define kblgt3__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define kblgt3__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define kblgt3__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define kblgt3__render_basic__sampler_l1_misses__read \ bdw__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define kblgt3__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define kblgt3__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define kblgt3__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define kblgt3__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define kblgt3__render_basic__l3_sampler_throughput__read \ bdw__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define kblgt3__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define kblgt3__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define kblgt3__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define kblgt3__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define kblgt3__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define kblgt3__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define kblgt3__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define kblgt3__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define kblgt3__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define kblgt3__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define kblgt3__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define kblgt3__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define kblgt3__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt3__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt3__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define kblgt3__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define kblgt3__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define kblgt3__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define kblgt3__render_basic__l3_lookups__read \ bdw__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define kblgt3__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define kblgt3__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define kblgt3__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define kblgt3__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define kblgt3__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define kblgt3__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define kblgt3__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define kblgt3__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define kblgt3__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define kblgt3__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define kblgt3__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define kblgt3__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define kblgt3__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define kblgt3__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define kblgt3__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define kblgt3__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define kblgt3__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define kblgt3__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define kblgt3__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define kblgt3__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define kblgt3__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define kblgt3__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define kblgt3__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define kblgt3__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define kblgt3__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define kblgt3__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define kblgt3__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define kblgt3__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define kblgt3__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define kblgt3__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define kblgt3__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define kblgt3__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define kblgt3__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define kblgt3__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define kblgt3__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define kblgt3__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define kblgt3__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define kblgt3__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define kblgt3__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define kblgt3__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define kblgt3__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define kblgt3__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define kblgt3__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define kblgt3__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define kblgt3__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define kblgt3__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define kblgt3__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define kblgt3__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define kblgt3__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define kblgt3__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define kblgt3__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define kblgt3__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define kblgt3__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define kblgt3__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define kblgt3__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define kblgt3__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define kblgt3__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define kblgt3__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define kblgt3__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define kblgt3__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define kblgt3__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define kblgt3__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define kblgt3__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define kblgt3__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define kblgt3__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define kblgt3__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define kblgt3__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define kblgt3__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define kblgt3__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define kblgt3__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define kblgt3__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define kblgt3__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define kblgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define kblgt3__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define kblgt3__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define kblgt3__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define kblgt3__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define kblgt3__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define kblgt3__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define kblgt3__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define kblgt3__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define kblgt3__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define kblgt3__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define kblgt3__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define kblgt3__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define kblgt3__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define kblgt3__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define kblgt3__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define kblgt3__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define kblgt3__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define kblgt3__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define kblgt3__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define kblgt3__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define kblgt3__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define kblgt3__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define kblgt3__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define kblgt3__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define kblgt3__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define kblgt3__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define kblgt3__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define kblgt3__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define kblgt3__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define kblgt3__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define kblgt3__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define kblgt3__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define kblgt3__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define kblgt3__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define kblgt3__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define kblgt3__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define kblgt3__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define kblgt3__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define kblgt3__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define kblgt3__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define kblgt3__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define kblgt3__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define kblgt3__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define kblgt3__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt3__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt3__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define kblgt3__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define kblgt3__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define kblgt3__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define kblgt3__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define kblgt3__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define kblgt3__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define kblgt3__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define kblgt3__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define kblgt3__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define kblgt3__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define kblgt3__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define kblgt3__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define kblgt3__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define kblgt3__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define kblgt3__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define kblgt3__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define kblgt3__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define kblgt3__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define kblgt3__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define kblgt3__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define kblgt3__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define kblgt3__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define kblgt3__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define kblgt3__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define kblgt3__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define kblgt3__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define kblgt3__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define kblgt3__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define kblgt3__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define kblgt3__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define kblgt3__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define kblgt3__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define kblgt3__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define kblgt3__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define kblgt3__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define kblgt3__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define kblgt3__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define kblgt3__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define kblgt3__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define kblgt3__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define kblgt3__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define kblgt3__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define kblgt3__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt3__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define kblgt3__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define kblgt3__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define kblgt3__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define kblgt3__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define kblgt3__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define kblgt3__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define kblgt3__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define kblgt3__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define kblgt3__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define kblgt3__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define kblgt3__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define kblgt3__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define kblgt3__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define kblgt3__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define kblgt3__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define kblgt3__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define kblgt3__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define kblgt3__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define kblgt3__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define kblgt3__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define kblgt3__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define kblgt3__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define kblgt3__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define kblgt3__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define kblgt3__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define kblgt3__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define kblgt3__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define kblgt3__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define kblgt3__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define kblgt3__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define kblgt3__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define kblgt3__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define kblgt3__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define kblgt3__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define kblgt3__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define kblgt3__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define kblgt3__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define kblgt3__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define kblgt3__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define kblgt3__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define kblgt3__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define kblgt3__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define kblgt3__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define kblgt3__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define kblgt3__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define kblgt3__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define kblgt3__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define kblgt3__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define kblgt3__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define kblgt3__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define kblgt3__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define kblgt3__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define kblgt3__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define kblgt3__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define kblgt3__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define kblgt3__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define kblgt3__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define kblgt3__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define kblgt3__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define kblgt3__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define kblgt3__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define kblgt3__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define kblgt3__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define kblgt3__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define kblgt3__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define kblgt3__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define kblgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define kblgt3__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define kblgt3__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define kblgt3__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define kblgt3__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define kblgt3__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define kblgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define kblgt3__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define kblgt3__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define kblgt3__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define kblgt3__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define kblgt3__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define kblgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define kblgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define kblgt3__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define kblgt3__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define kblgt3__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define kblgt3__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define kblgt3__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define kblgt3__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define kblgt3__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define kblgt3__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define kblgt3__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define kblgt3__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define kblgt3__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define kblgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define kblgt3__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define kblgt3__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define kblgt3__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define kblgt3__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define kblgt3__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define kblgt3__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define kblgt3__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define kblgt3__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define kblgt3__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define kblgt3__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define kblgt3__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define kblgt3__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define kblgt3__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define kblgt3__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define kblgt3__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define kblgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define kblgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define kblgt3__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define kblgt3__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define kblgt3__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define kblgt3__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define kblgt3__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define kblgt3__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define kblgt3__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define kblgt3__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define kblgt3__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define kblgt3__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define kblgt3__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define kblgt3__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define kblgt3__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define kblgt3__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define kblgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define kblgt3__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define kblgt3__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define kblgt3__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define kblgt3__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define kblgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define kblgt3__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define kblgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define kblgt3__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define kblgt3__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define kblgt3__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define kblgt3__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define kblgt3__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define kblgt3__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define kblgt3__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define kblgt3__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define kblgt3__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define kblgt3__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define kblgt3__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define kblgt3__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define kblgt3__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define kblgt3__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define kblgt3__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define kblgt3__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define kblgt3__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define kblgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define kblgt3__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define kblgt3__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define kblgt3__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define kblgt3__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define kblgt3__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define kblgt3__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define kblgt3__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define kblgt3__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define kblgt3__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define kblgt3__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define kblgt3__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define kblgt3__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define kblgt3__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define kblgt3__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define kblgt3__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define kblgt3__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define kblgt3__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define kblgt3__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define kblgt3__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define kblgt3__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define kblgt3__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define kblgt3__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define kblgt3__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define kblgt3__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define kblgt3__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define kblgt3__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define kblgt3__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define kblgt3__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define kblgt3__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define kblgt3__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define kblgt3__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define kblgt3__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define kblgt3__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define kblgt3__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define kblgt3__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define kblgt3__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define kblgt3__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define kblgt3__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define kblgt3__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define kblgt3__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define kblgt3__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define kblgt3__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define kblgt3__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define kblgt3__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define kblgt3__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define kblgt3__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define kblgt3__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define kblgt3__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define kblgt3__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define kblgt3__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define kblgt3__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define kblgt3__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define kblgt3__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define kblgt3__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define kblgt3__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define kblgt3__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define kblgt3__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define kblgt3__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define kblgt3__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define kblgt3__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define kblgt3__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define kblgt3__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define kblgt3__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define kblgt3__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define kblgt3__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define kblgt3__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define kblgt3__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define kblgt3__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define kblgt3__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define kblgt3__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define kblgt3__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define kblgt3__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define kblgt3__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define kblgt3__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define kblgt3__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define kblgt3__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define kblgt3__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define kblgt3__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define kblgt3__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define kblgt3__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define kblgt3__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define kblgt3__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define kblgt3__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define kblgt3__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define kblgt3__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define kblgt3__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define kblgt3__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define kblgt3__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define kblgt3__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define kblgt3__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define kblgt3__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define kblgt3__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define kblgt3__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define kblgt3__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define kblgt3__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define kblgt3__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define kblgt3__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define kblgt3__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define kblgt3__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define kblgt3__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define kblgt3__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define kblgt3__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define kblgt3__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define kblgt3__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define kblgt3__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define kblgt3__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define kblgt3__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define kblgt3__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define kblgt3__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define kblgt3__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define kblgt3__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define kblgt3__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define kblgt3__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define kblgt3__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define kblgt3__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define kblgt3__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define kblgt3__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define kblgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define kblgt3__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define kblgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define kblgt3__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define kblgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define kblgt3__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define kblgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define kblgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define kblgt3__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define kblgt3__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define kblgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define kblgt3__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define kblgt3__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define kblgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define kblgt3__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define kblgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define kblgt3__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define kblgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define kblgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define kblgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define kblgt3__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define kblgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define kblgt3__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define kblgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define kblgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define kblgt3__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define kblgt3__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define kblgt3__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define kblgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define kblgt3__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define kblgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define kblgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define kblgt3__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define kblgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define kblgt3__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define kblgt3__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define kblgt3__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define kblgt3__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define kblgt3__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define kblgt3__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define kblgt3__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define kblgt3__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define kblgt3__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define kblgt3__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define kblgt3__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define kblgt3__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define kblgt3__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define kblgt3__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define kblgt3__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define kblgt3__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define kblgt3__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define kblgt3__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define kblgt3__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define kblgt3__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define kblgt3__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define kblgt3__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define kblgt3__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define kblgt3__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define kblgt3__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define kblgt3__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define kblgt3__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define kblgt3__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define kblgt3__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define kblgt3__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define kblgt3__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define kblgt3__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define kblgt3__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define kblgt3__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define kblgt3__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define kblgt3__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define kblgt3__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define kblgt3__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define kblgt3__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define kblgt3__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define kblgt3__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define kblgt3__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define kblgt3__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define kblgt3__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define kblgt3__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define kblgt3__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define kblgt3__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define kblgt3__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define kblgt3__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define kblgt3__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define kblgt3__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define kblgt3__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define kblgt3__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define kblgt3__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define kblgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define kblgt3__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define kblgt3__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define kblgt3__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define kblgt3__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define kblgt3__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define kblgt3__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define kblgt3__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define kblgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define kblgt3__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define kblgt3__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define kblgt3__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define kblgt3__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define kblgt3__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define kblgt3__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define kblgt3__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define kblgt3__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define kblgt3__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define kblgt3__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define kblgt3__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define kblgt3__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define kblgt3__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define kblgt3__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define kblgt3__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define kblgt3__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define kblgt3__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define kblgt3__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define kblgt3__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define kblgt3__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define kblgt3__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define kblgt3__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define kblgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define kblgt3__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define kblgt3__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define kblgt3__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define kblgt3__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define kblgt3__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define kblgt3__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define kblgt3__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define kblgt3__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define kblgt3__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define kblgt3__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define kblgt3__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define kblgt3__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define kblgt3__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define kblgt3__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define kblgt3__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define kblgt3__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define kblgt3__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define kblgt3__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define kblgt3__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define kblgt3__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define kblgt3__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define kblgt3__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define kblgt3__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define kblgt3__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define kblgt3__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define kblgt3__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define kblgt3__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define kblgt3__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define kblgt3__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define kblgt3__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define kblgt3__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define kblgt3__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define kblgt3__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define kblgt3__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define kblgt3__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define kblgt3__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define kblgt3__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define kblgt3__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define kblgt3__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define kblgt3__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define kblgt3__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define kblgt3__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define kblgt3__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define kblgt3__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define kblgt3__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define kblgt3__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define kblgt3__compute_extra__fpu1_active_adjusted__read \ bdw__compute_extra__fpu1_active_adjusted__read /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define kblgt3__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define kblgt3__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define kblgt3__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define kblgt3__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define kblgt3__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define kblgt3__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define kblgt3__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define kblgt3__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define kblgt3__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define kblgt3__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define kblgt3__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define kblgt3__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define kblgt3__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define kblgt3__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define kblgt3__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define kblgt3__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define kblgt3__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define kblgt3__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define kblgt3__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__so_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define kblgt3__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* Gpu Rings Busyness :: Vdbox1 Ring Busy */ #define kblgt3__gpu_busyness__vdbox1_busy__read \ bdw__render_pipe_profile__sf_stall__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define kblgt3__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define kblgt3__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define kblgt3__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define kblgt3__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define kblgt3__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define kblgt3__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define kblgt3__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define kblgt3__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define kblgt3__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define kblgt3__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define kblgt3__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define kblgt3__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define kblgt3__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define kblgt3__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define kblgt3__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define kblgt3__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define kblgt3__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define kblgt3__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define cflgt2__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define cflgt2__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define cflgt2__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define cflgt2__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define cflgt2__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define cflgt2__render_basic__sampler_l1_misses__read \ sklgt2__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define cflgt2__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define cflgt2__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define cflgt2__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define cflgt2__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define cflgt2__render_basic__l3_sampler_throughput__read \ sklgt2__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define cflgt2__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define cflgt2__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define cflgt2__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define cflgt2__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define cflgt2__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define cflgt2__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define cflgt2__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define cflgt2__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define cflgt2__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define cflgt2__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define cflgt2__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define cflgt2__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define cflgt2__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt2__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt2__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define cflgt2__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define cflgt2__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define cflgt2__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define cflgt2__render_basic__l3_lookups__read \ sklgt2__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define cflgt2__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define cflgt2__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define cflgt2__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define cflgt2__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define cflgt2__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define cflgt2__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define cflgt2__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define cflgt2__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define cflgt2__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define cflgt2__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define cflgt2__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define cflgt2__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define cflgt2__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define cflgt2__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define cflgt2__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define cflgt2__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define cflgt2__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define cflgt2__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define cflgt2__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define cflgt2__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define cflgt2__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define cflgt2__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define cflgt2__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define cflgt2__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define cflgt2__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define cflgt2__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define cflgt2__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define cflgt2__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define cflgt2__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define cflgt2__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define cflgt2__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define cflgt2__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define cflgt2__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define cflgt2__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define cflgt2__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define cflgt2__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define cflgt2__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define cflgt2__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define cflgt2__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define cflgt2__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define cflgt2__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define cflgt2__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define cflgt2__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define cflgt2__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define cflgt2__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define cflgt2__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define cflgt2__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define cflgt2__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define cflgt2__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define cflgt2__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define cflgt2__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define cflgt2__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define cflgt2__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define cflgt2__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define cflgt2__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define cflgt2__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define cflgt2__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define cflgt2__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define cflgt2__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define cflgt2__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define cflgt2__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define cflgt2__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define cflgt2__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define cflgt2__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define cflgt2__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define cflgt2__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define cflgt2__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define cflgt2__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define cflgt2__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define cflgt2__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define cflgt2__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define cflgt2__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define cflgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define cflgt2__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define cflgt2__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define cflgt2__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define cflgt2__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define cflgt2__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define cflgt2__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define cflgt2__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define cflgt2__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define cflgt2__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define cflgt2__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define cflgt2__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define cflgt2__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define cflgt2__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define cflgt2__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define cflgt2__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define cflgt2__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define cflgt2__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define cflgt2__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define cflgt2__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define cflgt2__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define cflgt2__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define cflgt2__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define cflgt2__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define cflgt2__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define cflgt2__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define cflgt2__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define cflgt2__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define cflgt2__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define cflgt2__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define cflgt2__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define cflgt2__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define cflgt2__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define cflgt2__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define cflgt2__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define cflgt2__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define cflgt2__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define cflgt2__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define cflgt2__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define cflgt2__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define cflgt2__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define cflgt2__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define cflgt2__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define cflgt2__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define cflgt2__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt2__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt2__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define cflgt2__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define cflgt2__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define cflgt2__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define cflgt2__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define cflgt2__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define cflgt2__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define cflgt2__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define cflgt2__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define cflgt2__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define cflgt2__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define cflgt2__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define cflgt2__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define cflgt2__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define cflgt2__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define cflgt2__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define cflgt2__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define cflgt2__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define cflgt2__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define cflgt2__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define cflgt2__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define cflgt2__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define cflgt2__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define cflgt2__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define cflgt2__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define cflgt2__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define cflgt2__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define cflgt2__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define cflgt2__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define cflgt2__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define cflgt2__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define cflgt2__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define cflgt2__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define cflgt2__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define cflgt2__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define cflgt2__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define cflgt2__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define cflgt2__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define cflgt2__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define cflgt2__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define cflgt2__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define cflgt2__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define cflgt2__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define cflgt2__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt2__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt2__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define cflgt2__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define cflgt2__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define cflgt2__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define cflgt2__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define cflgt2__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define cflgt2__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define cflgt2__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define cflgt2__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define cflgt2__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define cflgt2__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define cflgt2__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define cflgt2__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define cflgt2__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define cflgt2__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define cflgt2__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define cflgt2__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define cflgt2__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define cflgt2__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define cflgt2__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define cflgt2__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define cflgt2__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define cflgt2__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define cflgt2__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define cflgt2__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define cflgt2__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define cflgt2__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define cflgt2__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define cflgt2__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define cflgt2__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define cflgt2__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define cflgt2__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define cflgt2__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define cflgt2__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define cflgt2__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define cflgt2__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define cflgt2__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define cflgt2__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define cflgt2__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define cflgt2__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define cflgt2__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define cflgt2__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define cflgt2__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define cflgt2__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define cflgt2__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define cflgt2__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define cflgt2__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define cflgt2__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define cflgt2__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define cflgt2__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define cflgt2__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define cflgt2__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define cflgt2__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define cflgt2__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define cflgt2__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define cflgt2__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define cflgt2__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define cflgt2__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define cflgt2__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define cflgt2__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define cflgt2__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define cflgt2__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define cflgt2__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define cflgt2__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define cflgt2__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define cflgt2__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define cflgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define cflgt2__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define cflgt2__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define cflgt2__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define cflgt2__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define cflgt2__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define cflgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define cflgt2__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define cflgt2__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define cflgt2__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define cflgt2__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define cflgt2__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define cflgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define cflgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define cflgt2__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define cflgt2__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define cflgt2__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define cflgt2__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define cflgt2__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define cflgt2__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define cflgt2__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define cflgt2__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define cflgt2__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define cflgt2__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define cflgt2__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define cflgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define cflgt2__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define cflgt2__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define cflgt2__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define cflgt2__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define cflgt2__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define cflgt2__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define cflgt2__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define cflgt2__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define cflgt2__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define cflgt2__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define cflgt2__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define cflgt2__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define cflgt2__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define cflgt2__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define cflgt2__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define cflgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define cflgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define cflgt2__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define cflgt2__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define cflgt2__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define cflgt2__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define cflgt2__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define cflgt2__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define cflgt2__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define cflgt2__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define cflgt2__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define cflgt2__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define cflgt2__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define cflgt2__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define cflgt2__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define cflgt2__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define cflgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define cflgt2__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define cflgt2__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define cflgt2__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define cflgt2__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define cflgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define cflgt2__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define cflgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define cflgt2__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define cflgt2__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define cflgt2__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define cflgt2__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define cflgt2__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define cflgt2__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define cflgt2__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define cflgt2__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define cflgt2__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define cflgt2__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define cflgt2__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define cflgt2__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define cflgt2__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define cflgt2__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define cflgt2__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define cflgt2__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define cflgt2__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define cflgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define cflgt2__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define cflgt2__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define cflgt2__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define cflgt2__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define cflgt2__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define cflgt2__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define cflgt2__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define cflgt2__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define cflgt2__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define cflgt2__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define cflgt2__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define cflgt2__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define cflgt2__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define cflgt2__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define cflgt2__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define cflgt2__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define cflgt2__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define cflgt2__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define cflgt2__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define cflgt2__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define cflgt2__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define cflgt2__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define cflgt2__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define cflgt2__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define cflgt2__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define cflgt2__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define cflgt2__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define cflgt2__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define cflgt2__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define cflgt2__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define cflgt2__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define cflgt2__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define cflgt2__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define cflgt2__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define cflgt2__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define cflgt2__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define cflgt2__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define cflgt2__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define cflgt2__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define cflgt2__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define cflgt2__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define cflgt2__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define cflgt2__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define cflgt2__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define cflgt2__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define cflgt2__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define cflgt2__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define cflgt2__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define cflgt2__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define cflgt2__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define cflgt2__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define cflgt2__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define cflgt2__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define cflgt2__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define cflgt2__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define cflgt2__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define cflgt2__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define cflgt2__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define cflgt2__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define cflgt2__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define cflgt2__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define cflgt2__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define cflgt2__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define cflgt2__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define cflgt2__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define cflgt2__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define cflgt2__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define cflgt2__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define cflgt2__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define cflgt2__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define cflgt2__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define cflgt2__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define cflgt2__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define cflgt2__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define cflgt2__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define cflgt2__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define cflgt2__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define cflgt2__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define cflgt2__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define cflgt2__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define cflgt2__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define cflgt2__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define cflgt2__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define cflgt2__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define cflgt2__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define cflgt2__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define cflgt2__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define cflgt2__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define cflgt2__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define cflgt2__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define cflgt2__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define cflgt2__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define cflgt2__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define cflgt2__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define cflgt2__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define cflgt2__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define cflgt2__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define cflgt2__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define cflgt2__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define cflgt2__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define cflgt2__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define cflgt2__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define cflgt2__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define cflgt2__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define cflgt2__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define cflgt2__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define cflgt2__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define cflgt2__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define cflgt2__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define cflgt2__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define cflgt2__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define cflgt2__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define cflgt2__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define cflgt2__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define cflgt2__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define cflgt2__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define cflgt2__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define cflgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define cflgt2__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define cflgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define cflgt2__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define cflgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define cflgt2__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define cflgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define cflgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define cflgt2__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define cflgt2__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define cflgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define cflgt2__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define cflgt2__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define cflgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define cflgt2__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define cflgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define cflgt2__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define cflgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define cflgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define cflgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define cflgt2__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define cflgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define cflgt2__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define cflgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define cflgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define cflgt2__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define cflgt2__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define cflgt2__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define cflgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define cflgt2__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define cflgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define cflgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define cflgt2__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define cflgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define cflgt2__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define cflgt2__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define cflgt2__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define cflgt2__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define cflgt2__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define cflgt2__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define cflgt2__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define cflgt2__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define cflgt2__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define cflgt2__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define cflgt2__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define cflgt2__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define cflgt2__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define cflgt2__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define cflgt2__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define cflgt2__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define cflgt2__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define cflgt2__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define cflgt2__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define cflgt2__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define cflgt2__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define cflgt2__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define cflgt2__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define cflgt2__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define cflgt2__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define cflgt2__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define cflgt2__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define cflgt2__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define cflgt2__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define cflgt2__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define cflgt2__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define cflgt2__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define cflgt2__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define cflgt2__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define cflgt2__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define cflgt2__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define cflgt2__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define cflgt2__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define cflgt2__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define cflgt2__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define cflgt2__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define cflgt2__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define cflgt2__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define cflgt2__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define cflgt2__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define cflgt2__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define cflgt2__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define cflgt2__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define cflgt2__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define cflgt2__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define cflgt2__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define cflgt2__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define cflgt2__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define cflgt2__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define cflgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define cflgt2__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define cflgt2__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define cflgt2__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define cflgt2__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define cflgt2__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define cflgt2__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define cflgt2__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define cflgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define cflgt2__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define cflgt2__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define cflgt2__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define cflgt2__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define cflgt2__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define cflgt2__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define cflgt2__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define cflgt2__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define cflgt2__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define cflgt2__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define cflgt2__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define cflgt2__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define cflgt2__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define cflgt2__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define cflgt2__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define cflgt2__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define cflgt2__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define cflgt2__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define cflgt2__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define cflgt2__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define cflgt2__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define cflgt2__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define cflgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define cflgt2__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define cflgt2__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define cflgt2__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define cflgt2__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define cflgt2__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define cflgt2__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define cflgt2__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define cflgt2__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define cflgt2__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define cflgt2__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define cflgt2__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define cflgt2__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define cflgt2__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define cflgt2__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define cflgt2__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define cflgt2__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define cflgt2__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define cflgt2__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define cflgt2__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define cflgt2__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define cflgt2__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define cflgt2__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define cflgt2__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define cflgt2__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define cflgt2__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define cflgt2__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define cflgt2__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define cflgt2__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define cflgt2__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define cflgt2__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define cflgt2__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define cflgt2__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define cflgt2__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define cflgt2__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define cflgt2__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define cflgt2__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define cflgt2__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define cflgt2__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define cflgt2__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define cflgt2__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define cflgt2__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define cflgt2__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define cflgt2__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define cflgt2__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define cflgt2__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define cflgt2__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define cflgt2__compute_extra__fpu1_active_adjusted__read \ sklgt2__compute_extra__fpu1_active_adjusted__read /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define cflgt2__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define cflgt2__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define cflgt2__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define cflgt2__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define cflgt2__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define cflgt2__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define cflgt2__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define cflgt2__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define cflgt2__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define cflgt2__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define cflgt2__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define cflgt2__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define cflgt2__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__sf_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define cflgt2__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define cflgt2__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define cflgt2__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define cflgt2__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define cflgt2__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define cflgt2__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define cflgt2__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* MDAPI testing set Gen9.5 :: TestCounter7 */ #define cflgt2__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9.5 :: GPU Time Elapsed */ #define cflgt2__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9.5 :: GPU Core Clocks */ #define cflgt2__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ #define cflgt2__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ #define cflgt2__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9.5 :: TestCounter8 */ #define cflgt2__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9.5 :: TestCounter4 */ #define cflgt2__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9.5 :: TestCounter5 */ #define cflgt2__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9.5 :: TestCounter6 */ #define cflgt2__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9.5 :: TestCounter3 */ #define cflgt2__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9.5 :: TestCounter0 */ #define cflgt2__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9.5 :: TestCounter1 */ #define cflgt2__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9.5 :: TestCounter2 */ #define cflgt2__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define cflgt2__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define cflgt2__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define cflgt2__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define cflgt2__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define cflgt2__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define cflgt3__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define cflgt3__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define cflgt3__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define cflgt3__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define cflgt3__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define cflgt3__render_basic__sampler_l1_misses__read \ bdw__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define cflgt3__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define cflgt3__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define cflgt3__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define cflgt3__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define cflgt3__render_basic__l3_sampler_throughput__read \ bdw__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define cflgt3__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define cflgt3__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define cflgt3__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define cflgt3__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define cflgt3__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define cflgt3__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define cflgt3__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define cflgt3__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define cflgt3__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define cflgt3__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define cflgt3__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define cflgt3__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define cflgt3__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt3__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt3__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define cflgt3__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define cflgt3__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define cflgt3__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define cflgt3__render_basic__l3_lookups__read \ bdw__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define cflgt3__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define cflgt3__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define cflgt3__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define cflgt3__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define cflgt3__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define cflgt3__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define cflgt3__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define cflgt3__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define cflgt3__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define cflgt3__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define cflgt3__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define cflgt3__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define cflgt3__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define cflgt3__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define cflgt3__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define cflgt3__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define cflgt3__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define cflgt3__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define cflgt3__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define cflgt3__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define cflgt3__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define cflgt3__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define cflgt3__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define cflgt3__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define cflgt3__compute_basic__untyped_bytes_read__read \ bdw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define cflgt3__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define cflgt3__compute_basic__typed_bytes_written__read \ bdw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define cflgt3__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define cflgt3__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define cflgt3__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define cflgt3__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define cflgt3__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define cflgt3__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define cflgt3__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define cflgt3__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define cflgt3__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define cflgt3__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define cflgt3__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define cflgt3__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define cflgt3__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define cflgt3__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define cflgt3__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define cflgt3__compute_basic__untyped_bytes_written__read \ bdw__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define cflgt3__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define cflgt3__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define cflgt3__compute_basic__typed_bytes_read__read \ bdw__compute_basic__typed_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define cflgt3__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define cflgt3__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define cflgt3__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define cflgt3__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define cflgt3__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define cflgt3__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define cflgt3__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define cflgt3__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define cflgt3__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define cflgt3__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define cflgt3__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define cflgt3__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define cflgt3__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define cflgt3__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define cflgt3__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define cflgt3__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define cflgt3__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define cflgt3__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define cflgt3__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define cflgt3__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define cflgt3__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define cflgt3__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define cflgt3__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define cflgt3__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define cflgt3__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define cflgt3__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define cflgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define cflgt3__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define cflgt3__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define cflgt3__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define cflgt3__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define cflgt3__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define cflgt3__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define cflgt3__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define cflgt3__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define cflgt3__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define cflgt3__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define cflgt3__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define cflgt3__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define cflgt3__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define cflgt3__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define cflgt3__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define cflgt3__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define cflgt3__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define cflgt3__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define cflgt3__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define cflgt3__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define cflgt3__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define cflgt3__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define cflgt3__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define cflgt3__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define cflgt3__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define cflgt3__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define cflgt3__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define cflgt3__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define cflgt3__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define cflgt3__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define cflgt3__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define cflgt3__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define cflgt3__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define cflgt3__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define cflgt3__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define cflgt3__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define cflgt3__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define cflgt3__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define cflgt3__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define cflgt3__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define cflgt3__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define cflgt3__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define cflgt3__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define cflgt3__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt3__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt3__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define cflgt3__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define cflgt3__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define cflgt3__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define cflgt3__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define cflgt3__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define cflgt3__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define cflgt3__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define cflgt3__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define cflgt3__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define cflgt3__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define cflgt3__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define cflgt3__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define cflgt3__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define cflgt3__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define cflgt3__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define cflgt3__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define cflgt3__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define cflgt3__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define cflgt3__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define cflgt3__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define cflgt3__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define cflgt3__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define cflgt3__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define cflgt3__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define cflgt3__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define cflgt3__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define cflgt3__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define cflgt3__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define cflgt3__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define cflgt3__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define cflgt3__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define cflgt3__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define cflgt3__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define cflgt3__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define cflgt3__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define cflgt3__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define cflgt3__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define cflgt3__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define cflgt3__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define cflgt3__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define cflgt3__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define cflgt3__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define cflgt3__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt3__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define cflgt3__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define cflgt3__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define cflgt3__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define cflgt3__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define cflgt3__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define cflgt3__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define cflgt3__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define cflgt3__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define cflgt3__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define cflgt3__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define cflgt3__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define cflgt3__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define cflgt3__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define cflgt3__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define cflgt3__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define cflgt3__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define cflgt3__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define cflgt3__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define cflgt3__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define cflgt3__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define cflgt3__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define cflgt3__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define cflgt3__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define cflgt3__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define cflgt3__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define cflgt3__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define cflgt3__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define cflgt3__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define cflgt3__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define cflgt3__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define cflgt3__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define cflgt3__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define cflgt3__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define cflgt3__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define cflgt3__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define cflgt3__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define cflgt3__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define cflgt3__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define cflgt3__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define cflgt3__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define cflgt3__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define cflgt3__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define cflgt3__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define cflgt3__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define cflgt3__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define cflgt3__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define cflgt3__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define cflgt3__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define cflgt3__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define cflgt3__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define cflgt3__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define cflgt3__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define cflgt3__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define cflgt3__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define cflgt3__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define cflgt3__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define cflgt3__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define cflgt3__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define cflgt3__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define cflgt3__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define cflgt3__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define cflgt3__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define cflgt3__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define cflgt3__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define cflgt3__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define cflgt3__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define cflgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define cflgt3__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define cflgt3__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define cflgt3__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define cflgt3__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define cflgt3__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define cflgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define cflgt3__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define cflgt3__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define cflgt3__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define cflgt3__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define cflgt3__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define cflgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define cflgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define cflgt3__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define cflgt3__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define cflgt3__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define cflgt3__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define cflgt3__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define cflgt3__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define cflgt3__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define cflgt3__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define cflgt3__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define cflgt3__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define cflgt3__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define cflgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define cflgt3__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define cflgt3__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define cflgt3__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define cflgt3__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define cflgt3__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define cflgt3__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define cflgt3__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define cflgt3__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define cflgt3__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define cflgt3__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define cflgt3__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define cflgt3__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define cflgt3__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define cflgt3__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define cflgt3__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define cflgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define cflgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define cflgt3__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define cflgt3__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define cflgt3__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define cflgt3__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define cflgt3__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define cflgt3__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define cflgt3__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define cflgt3__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define cflgt3__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define cflgt3__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define cflgt3__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define cflgt3__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define cflgt3__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define cflgt3__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define cflgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define cflgt3__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define cflgt3__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define cflgt3__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define cflgt3__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define cflgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define cflgt3__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ #define cflgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define cflgt3__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define cflgt3__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define cflgt3__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define cflgt3__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define cflgt3__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define cflgt3__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define cflgt3__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define cflgt3__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define cflgt3__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define cflgt3__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define cflgt3__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define cflgt3__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define cflgt3__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define cflgt3__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define cflgt3__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define cflgt3__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define cflgt3__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define cflgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define cflgt3__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define cflgt3__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define cflgt3__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define cflgt3__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define cflgt3__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define cflgt3__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define cflgt3__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define cflgt3__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define cflgt3__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define cflgt3__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define cflgt3__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define cflgt3__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define cflgt3__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define cflgt3__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define cflgt3__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define cflgt3__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define cflgt3__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define cflgt3__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define cflgt3__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define cflgt3__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define cflgt3__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define cflgt3__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define cflgt3__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define cflgt3__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define cflgt3__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define cflgt3__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define cflgt3__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define cflgt3__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define cflgt3__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define cflgt3__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define cflgt3__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define cflgt3__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define cflgt3__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define cflgt3__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define cflgt3__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define cflgt3__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define cflgt3__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define cflgt3__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define cflgt3__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define cflgt3__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define cflgt3__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define cflgt3__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define cflgt3__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define cflgt3__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: VS Send Pipe Active */ #define cflgt3__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define cflgt3__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define cflgt3__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define cflgt3__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define cflgt3__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define cflgt3__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define cflgt3__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define cflgt3__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Sampler Texels */ #define cflgt3__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define cflgt3__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define cflgt3__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define cflgt3__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define cflgt3__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define cflgt3__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define cflgt3__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define cflgt3__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define cflgt3__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define cflgt3__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define cflgt3__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define cflgt3__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define cflgt3__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice0 L3 Bank2 Active */ #define cflgt3__l3_2__l30_bank2_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: Rasterized Pixels */ #define cflgt3__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define cflgt3__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define cflgt3__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define cflgt3__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define cflgt3__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Samples Blended */ #define cflgt3__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define cflgt3__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define cflgt3__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define cflgt3__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: SLM Bytes Written */ #define cflgt3__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: L3 Shader Throughput */ #define cflgt3__l3_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define cflgt3__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define cflgt3__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_3 :: GPU Core Clocks */ #define cflgt3__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_3 :: EU Active */ #define cflgt3__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_3 :: EU Both FPU Pipes Active */ #define cflgt3__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_3 :: VS Send Pipe Active */ #define cflgt3__l3_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_3 :: VS FPU1 Pipe Active */ #define cflgt3__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_3 :: GS Threads Dispatched */ #define cflgt3__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_3 :: Early Hi-Depth Test Fails */ #define cflgt3__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_3 :: FS Both FPU Active */ #define cflgt3__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_3 :: VS Threads Dispatched */ #define cflgt3__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_3 :: FS Threads Dispatched */ #define cflgt3__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ #define cflgt3__l3_3__l30_bank3_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_3 :: Shader Barrier Messages */ #define cflgt3__l3_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Sampler Texels */ #define cflgt3__l3_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_3 :: Pixels Failing Tests */ #define cflgt3__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_3 :: GPU Time Elapsed */ #define cflgt3__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define cflgt3__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_3 :: AVG GPU Core Frequency */ #define cflgt3__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_3 :: Sampler Texels Misses */ #define cflgt3__l3_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_3 :: CS Threads Dispatched */ #define cflgt3__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_3 :: SLM Bytes Read */ #define cflgt3__l3_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_3 :: PS FPU1 Pipe Active */ #define cflgt3__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_3 :: Slice0 L3 Bank3 Active */ #define cflgt3__l3_3__l30_bank3_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_3 :: PS Send Pipeline Active */ #define cflgt3__l3_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_3 :: VS FPU0 Pipe Active */ #define cflgt3__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_3 :: GPU Busy */ #define cflgt3__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_3 :: Rasterized Pixels */ #define cflgt3__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_3 :: PS FPU0 Pipe Active */ #define cflgt3__l3_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_3 :: DS Threads Dispatched */ #define cflgt3__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_3 :: Samples Written */ #define cflgt3__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_3 :: EU Stall */ #define cflgt3__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_3 :: Samples Blended */ #define cflgt3__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_3 :: Early Depth Test Fails */ #define cflgt3__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_3 :: Shader Memory Accesses */ #define cflgt3__l3_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_3 :: HS Threads Dispatched */ #define cflgt3__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_3 :: SLM Bytes Written */ #define cflgt3__l3_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_3 :: L3 Shader Throughput */ #define cflgt3__l3_3__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_3 :: Samples Killed in FS */ #define cflgt3__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_3 :: Shader Atomic Memory Accesses */ #define cflgt3__l3_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define cflgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define cflgt3__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define cflgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define cflgt3__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define cflgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define cflgt3__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define cflgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define cflgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define cflgt3__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define cflgt3__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define cflgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define cflgt3__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define cflgt3__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define cflgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define cflgt3__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define cflgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define cflgt3__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define cflgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define cflgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define cflgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define cflgt3__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define cflgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define cflgt3__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define cflgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define cflgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define cflgt3__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define cflgt3__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define cflgt3__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define cflgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define cflgt3__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define cflgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define cflgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define cflgt3__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define cflgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define cflgt3__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define cflgt3__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define cflgt3__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define cflgt3__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define cflgt3__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define cflgt3__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define cflgt3__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define cflgt3__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define cflgt3__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define cflgt3__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define cflgt3__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define cflgt3__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define cflgt3__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define cflgt3__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define cflgt3__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define cflgt3__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define cflgt3__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define cflgt3__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define cflgt3__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define cflgt3__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define cflgt3__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define cflgt3__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define cflgt3__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define cflgt3__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define cflgt3__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define cflgt3__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define cflgt3__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define cflgt3__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define cflgt3__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define cflgt3__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define cflgt3__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define cflgt3__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define cflgt3__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define cflgt3__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define cflgt3__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define cflgt3__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define cflgt3__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define cflgt3__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define cflgt3__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define cflgt3__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define cflgt3__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define cflgt3__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define cflgt3__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define cflgt3__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define cflgt3__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define cflgt3__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define cflgt3__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define cflgt3__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define cflgt3__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define cflgt3__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define cflgt3__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define cflgt3__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define cflgt3__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define cflgt3__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define cflgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define cflgt3__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define cflgt3__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define cflgt3__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define cflgt3__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define cflgt3__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define cflgt3__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define cflgt3__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define cflgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define cflgt3__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define cflgt3__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define cflgt3__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define cflgt3__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define cflgt3__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define cflgt3__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define cflgt3__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define cflgt3__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define cflgt3__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define cflgt3__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define cflgt3__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define cflgt3__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define cflgt3__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define cflgt3__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define cflgt3__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define cflgt3__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define cflgt3__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define cflgt3__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define cflgt3__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define cflgt3__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define cflgt3__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define cflgt3__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define cflgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define cflgt3__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define cflgt3__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define cflgt3__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define cflgt3__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define cflgt3__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define cflgt3__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define cflgt3__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define cflgt3__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define cflgt3__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define cflgt3__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define cflgt3__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define cflgt3__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define cflgt3__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define cflgt3__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define cflgt3__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define cflgt3__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define cflgt3__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define cflgt3__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define cflgt3__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define cflgt3__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define cflgt3__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define cflgt3__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define cflgt3__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define cflgt3__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define cflgt3__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define cflgt3__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define cflgt3__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define cflgt3__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define cflgt3__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define cflgt3__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define cflgt3__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define cflgt3__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define cflgt3__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define cflgt3__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define cflgt3__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define cflgt3__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define cflgt3__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define cflgt3__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define cflgt3__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define cflgt3__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define cflgt3__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define cflgt3__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define cflgt3__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define cflgt3__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define cflgt3__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define cflgt3__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define cflgt3__compute_extra__fpu1_active_adjusted__read \ bdw__compute_extra__fpu1_active_adjusted__read /* Media Vme Pipe Gen9 :: GPU Core Clocks */ #define cflgt3__vme_pipe__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Media Vme Pipe Gen9 :: EU Active */ #define cflgt3__vme_pipe__eu_active__read \ bdw__render_basic__eu_active__read /* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ #define cflgt3__vme_pipe__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Media Vme Pipe Gen9 :: GPU Time Elapsed */ #define cflgt3__vme_pipe__gpu_time__read \ hsw__render_basic__gpu_time__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define cflgt3__vme_pipe__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ #define cflgt3__vme_pipe__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Media Vme Pipe Gen9 :: CS Threads Dispatched */ #define cflgt3__vme_pipe__cs_threads__read \ bdw__render_basic__cs_threads__read /* Media Vme Pipe Gen9 :: EU Thread Occupancy */ #define cflgt3__vme_pipe__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Media Vme Pipe Gen9 :: EU Stall */ #define cflgt3__vme_pipe__eu_stall__read \ bdw__render_basic__eu_stall__read /* Media Vme Pipe Gen9 :: VME Busy */ #define cflgt3__vme_pipe__vme_busy__read \ bdw__vme_pipe__vme_busy__read /* Media Vme Pipe Gen9 :: GPU Busy */ #define cflgt3__vme_pipe__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define cflgt3__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define cflgt3__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define cflgt3__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define cflgt3__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define cflgt3__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define cflgt3__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define cflgt3__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define cflgt3__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__so_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define cflgt3__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* Gpu Rings Busyness :: Vdbox1 Ring Busy */ #define cflgt3__gpu_busyness__vdbox1_busy__read \ bdw__render_pipe_profile__sf_stall__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define cflgt3__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define cflgt3__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define cflgt3__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define cflgt3__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define cflgt3__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define cflgt3__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define cflgt3__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define cflgt3__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define cflgt3__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define cflgt3__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define cflgt3__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define cflgt3__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define cflgt3__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define cflgt3__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define cflgt3__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define cflgt3__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define cflgt3__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define cflgt3__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define bxt__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define bxt__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define bxt__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define bxt__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define bxt__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define bxt__render_basic__sampler_l1_misses__read \ sklgt2__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define bxt__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define bxt__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define bxt__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define bxt__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define bxt__render_basic__l3_sampler_throughput__read \ sklgt2__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define bxt__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define bxt__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define bxt__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define bxt__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define bxt__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define bxt__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define bxt__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define bxt__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define bxt__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define bxt__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define bxt__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define bxt__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define bxt__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define bxt__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define bxt__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define bxt__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define bxt__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define bxt__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define bxt__render_basic__l3_lookups__read \ sklgt2__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define bxt__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define bxt__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define bxt__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define bxt__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define bxt__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define bxt__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define bxt__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define bxt__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define bxt__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define bxt__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define bxt__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define bxt__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define bxt__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define bxt__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define bxt__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define bxt__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define bxt__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define bxt__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define bxt__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define bxt__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define bxt__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define bxt__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define bxt__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define bxt__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define bxt__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define bxt__compute_basic__untyped_bytes_read__read \ hsw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define bxt__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ static uint64_t bxt__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ B 4 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = accumulator[query->b_offset + 4]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define bxt__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define bxt__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define bxt__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define bxt__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define bxt__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define bxt__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define bxt__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define bxt__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define bxt__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define bxt__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define bxt__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define bxt__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define bxt__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define bxt__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define bxt__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ static uint64_t bxt__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ C 2 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = accumulator[query->c_offset + 2]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = perf->sys_vars.n_eu_slices * 64; uint64_t tmp4 = tmp2 * tmp3; return tmp4; } /* Compute Metrics Basic Gen9 :: GPU Busy */ #define bxt__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define bxt__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define bxt__compute_basic__typed_bytes_read__read \ hsw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define bxt__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define bxt__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define bxt__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define bxt__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define bxt__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define bxt__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define bxt__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define bxt__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define bxt__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define bxt__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define bxt__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define bxt__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define bxt__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define bxt__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define bxt__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define bxt__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define bxt__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define bxt__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define bxt__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define bxt__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define bxt__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define bxt__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define bxt__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define bxt__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define bxt__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define bxt__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define bxt__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define bxt__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define bxt__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define bxt__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define bxt__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define bxt__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define bxt__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define bxt__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define bxt__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define bxt__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define bxt__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define bxt__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define bxt__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define bxt__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define bxt__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define bxt__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define bxt__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define bxt__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define bxt__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define bxt__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define bxt__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define bxt__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define bxt__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define bxt__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define bxt__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define bxt__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define bxt__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define bxt__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define bxt__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define bxt__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define bxt__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define bxt__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define bxt__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define bxt__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define bxt__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define bxt__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define bxt__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define bxt__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define bxt__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define bxt__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define bxt__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define bxt__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define bxt__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define bxt__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define bxt__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define bxt__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define bxt__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define bxt__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define bxt__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define bxt__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define bxt__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define bxt__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define bxt__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define bxt__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define bxt__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define bxt__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define bxt__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define bxt__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define bxt__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define bxt__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define bxt__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define bxt__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define bxt__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define bxt__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define bxt__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define bxt__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define bxt__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define bxt__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define bxt__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define bxt__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define bxt__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define bxt__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define bxt__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define bxt__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define bxt__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define bxt__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define bxt__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define bxt__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define bxt__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define bxt__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define bxt__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define bxt__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define bxt__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define bxt__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define bxt__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define bxt__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define bxt__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define bxt__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define bxt__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define bxt__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define bxt__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define bxt__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define bxt__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define bxt__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define bxt__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define bxt__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define bxt__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define bxt__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define bxt__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define bxt__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define bxt__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define bxt__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define bxt__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define bxt__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define bxt__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define bxt__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define bxt__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define bxt__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define bxt__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define bxt__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define bxt__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define bxt__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define bxt__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define bxt__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define bxt__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define bxt__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define bxt__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define bxt__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define bxt__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define bxt__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define bxt__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define bxt__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define bxt__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define bxt__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define bxt__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define bxt__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define bxt__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define bxt__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define bxt__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define bxt__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define bxt__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define bxt__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define bxt__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define bxt__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define bxt__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define bxt__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define bxt__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define bxt__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define bxt__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define bxt__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define bxt__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define bxt__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define bxt__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define bxt__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define bxt__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define bxt__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define bxt__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define bxt__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define bxt__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define bxt__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define bxt__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define bxt__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define bxt__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define bxt__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define bxt__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define bxt__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define bxt__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define bxt__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define bxt__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define bxt__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define bxt__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define bxt__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define bxt__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define bxt__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define bxt__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define bxt__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define bxt__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define bxt__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define bxt__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define bxt__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define bxt__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define bxt__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define bxt__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define bxt__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define bxt__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define bxt__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define bxt__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define bxt__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define bxt__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define bxt__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define bxt__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define bxt__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define bxt__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define bxt__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define bxt__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define bxt__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define bxt__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define bxt__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define bxt__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define bxt__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define bxt__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define bxt__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define bxt__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define bxt__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define bxt__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define bxt__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define bxt__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define bxt__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define bxt__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define bxt__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define bxt__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define bxt__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define bxt__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define bxt__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define bxt__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define bxt__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define bxt__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define bxt__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define bxt__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define bxt__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define bxt__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define bxt__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define bxt__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define bxt__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define bxt__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define bxt__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define bxt__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define bxt__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define bxt__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define bxt__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define bxt__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define bxt__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define bxt__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define bxt__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define bxt__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define bxt__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define bxt__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define bxt__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define bxt__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define bxt__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define bxt__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define bxt__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define bxt__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define bxt__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define bxt__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define bxt__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define bxt__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define bxt__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define bxt__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define bxt__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define bxt__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define bxt__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define bxt__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define bxt__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define bxt__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define bxt__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define bxt__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define bxt__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define bxt__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define bxt__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define bxt__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define bxt__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define bxt__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define bxt__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define bxt__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define bxt__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define bxt__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define bxt__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define bxt__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define bxt__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define bxt__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define bxt__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define bxt__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define bxt__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define bxt__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define bxt__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define bxt__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define bxt__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define bxt__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define bxt__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define bxt__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define bxt__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define bxt__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define bxt__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define bxt__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define bxt__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define bxt__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define bxt__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define bxt__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define bxt__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define bxt__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define bxt__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define bxt__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define bxt__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define bxt__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define bxt__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define bxt__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define bxt__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define bxt__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define bxt__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define bxt__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define bxt__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define bxt__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define bxt__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define bxt__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define bxt__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define bxt__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define bxt__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define bxt__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define bxt__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define bxt__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define bxt__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define bxt__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define bxt__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define bxt__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define bxt__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define bxt__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define bxt__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define bxt__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define bxt__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define bxt__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define bxt__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define bxt__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define bxt__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define bxt__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define bxt__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define bxt__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define bxt__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define bxt__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define bxt__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define bxt__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define bxt__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define bxt__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define bxt__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define bxt__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define bxt__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define bxt__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define bxt__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define bxt__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define bxt__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define bxt__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define bxt__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define bxt__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define bxt__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define bxt__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define bxt__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define bxt__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define bxt__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define bxt__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define bxt__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define bxt__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define bxt__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define bxt__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define bxt__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define bxt__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define bxt__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define bxt__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define bxt__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define bxt__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define bxt__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define bxt__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define bxt__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define bxt__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define bxt__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define bxt__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define bxt__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define bxt__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define bxt__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define bxt__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define bxt__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define bxt__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define bxt__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define bxt__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define bxt__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define bxt__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define bxt__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define bxt__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define bxt__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define bxt__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define bxt__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define bxt__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define bxt__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define bxt__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define bxt__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define bxt__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define bxt__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define bxt__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define bxt__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define bxt__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define bxt__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define bxt__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define bxt__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define bxt__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define bxt__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define bxt__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define bxt__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define bxt__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define bxt__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define bxt__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define bxt__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define bxt__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define bxt__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define bxt__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define bxt__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define bxt__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define bxt__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define bxt__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define bxt__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define bxt__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define bxt__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define bxt__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define bxt__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define bxt__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define bxt__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define bxt__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define bxt__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define bxt__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define bxt__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define bxt__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define bxt__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define bxt__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define bxt__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define bxt__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define bxt__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define bxt__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define bxt__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define bxt__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define bxt__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define bxt__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define bxt__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define bxt__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define bxt__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define bxt__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define bxt__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define bxt__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define bxt__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define bxt__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define bxt__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define bxt__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define bxt__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define bxt__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define bxt__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define bxt__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define bxt__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define bxt__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define bxt__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define bxt__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define bxt__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define bxt__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define bxt__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define bxt__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define bxt__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define bxt__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define bxt__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define bxt__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define bxt__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define bxt__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define bxt__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define bxt__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define bxt__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define bxt__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define bxt__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define bxt__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define bxt__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define bxt__compute_extra__fpu1_active_adjusted__read \ sklgt2__compute_extra__fpu1_active_adjusted__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define bxt__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define bxt__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__sf_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define bxt__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define bxt__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define bxt__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define bxt__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define bxt__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define bxt__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define bxt__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define bxt__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define bxt__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define bxt__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define bxt__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define bxt__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define bxt__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define bxt__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define bxt__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define bxt__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define bxt__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define bxt__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define bxt__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define bxt__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define bxt__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define bxt__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define bxt__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define bxt__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define bxt__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: GPU Core Clocks */ #define glk__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen9 :: EU Active */ #define glk__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen9 :: L3 Misses */ #define glk__render_basic__l3_misses__read \ hsw__compute_extended__typed_atomics0__read /* Render Metrics Basic Gen9 :: GTI L3 Throughput */ #define glk__render_basic__gti_l3_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define glk__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen9 :: Sampler Cache Misses */ #define glk__render_basic__sampler_l1_misses__read \ sklgt2__render_basic__sampler_l1_misses__read /* Render Metrics Basic Gen9 :: VS Send Pipe Active */ #define glk__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ #define glk__render_basic__sampler1_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ #define glk__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen9 :: GS Threads Dispatched */ #define glk__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ #define glk__render_basic__l3_sampler_throughput__read \ sklgt2__render_basic__l3_sampler_throughput__read /* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define glk__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen9 :: FS Both FPU Active */ #define glk__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen9 :: VS Threads Dispatched */ #define glk__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen9 :: FS Threads Dispatched */ #define glk__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen9 :: Sampler 0 Busy */ #define glk__render_basic__sampler0_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen9 :: Sampler 1 Busy */ #define glk__render_basic__sampler1_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen9 :: Samplers Busy */ #define glk__render_basic__samplers_busy__read \ bdw__render_basic__samplers_busy__read /* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ #define glk__render_basic__gti_vf_throughput__read \ bdw__render_basic__gti_vf_throughput__read /* Render Metrics Basic Gen9 :: Shader Barrier Messages */ #define glk__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ #define glk__render_basic__sampler0_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen9 :: Sampler Texels */ #define glk__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen9 :: Pixels Failing Tests */ #define glk__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen9 :: GPU Time Elapsed */ #define glk__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define glk__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define glk__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen9 :: Sampler Texels Misses */ #define glk__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen9 :: CS Threads Dispatched */ #define glk__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen9 :: Shader Memory Accesses */ #define glk__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ #define glk__render_basic__l3_lookups__read \ sklgt2__render_basic__l3_lookups__read /* Render Metrics Basic Gen9 :: SLM Bytes Read */ #define glk__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen9 :: GTI Read Throughput */ #define glk__render_basic__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ #define glk__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ #define glk__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen9 :: Rasterized Pixels */ #define glk__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen9 :: GPU Busy */ #define glk__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen9 :: GTI Depth Throughput */ #define glk__render_basic__gti_depth_throughput__read \ bdw__render_basic__gti_depth_throughput__read /* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ #define glk__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ #define glk__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen9 :: DS Threads Dispatched */ #define glk__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen9 :: Samples Written */ #define glk__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen9 :: EU Stall */ #define glk__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen9 :: Samples Blended */ #define glk__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen9 :: Early Depth Test Fails */ #define glk__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen9 :: Samplers Bottleneck */ #define glk__render_basic__sampler_bottleneck__read \ bdw__render_basic__sampler_bottleneck__read /* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ #define glk__render_basic__gti_hdc_lookups_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Render Metrics Basic Gen9 :: GTI RCC Throughput */ #define glk__render_basic__gti_rcc_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen9 :: HS Threads Dispatched */ #define glk__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen9 :: GTI Write Throughput */ #define glk__render_basic__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Render Metrics Basic Gen9 :: SLM Bytes Written */ #define glk__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen9 :: L3 Shader Throughput */ #define glk__render_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics Basic Gen9 :: Samples Killed in FS */ #define glk__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define glk__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: GPU Core Clocks */ #define glk__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen9 :: EU Active */ #define glk__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ #define glk__compute_basic__untyped_bytes_read__read \ hsw__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ #define glk__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen9 :: Typed Bytes Written */ #define glk__compute_basic__typed_bytes_written__read \ bxt__compute_basic__typed_bytes_written__read /* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ #define glk__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ #define glk__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ #define glk__compute_basic__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ #define glk__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ #define glk__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ #define glk__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ #define glk__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ #define glk__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Sampler Texels */ #define glk__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ #define glk__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ #define glk__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define glk__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ #define glk__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ #define glk__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ #define glk__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen9 :: SLM Bytes Read */ #define glk__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen9 :: GTI Read Throughput */ #define glk__compute_basic__gti_read_throughput__read \ hsw__render_basic__gti_l3_throughput__read /* Compute Metrics Basic Gen9 :: Untyped Writes */ #define glk__compute_basic__untyped_bytes_written__read \ bxt__compute_basic__untyped_bytes_written__read /* Compute Metrics Basic Gen9 :: GPU Busy */ #define glk__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen9 :: Rasterized Pixels */ #define glk__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen9 :: Typed Bytes Read */ #define glk__compute_basic__typed_bytes_read__read \ hsw__compute_basic__untyped_bytes_read__read /* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ #define glk__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ #define glk__compute_basic__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen9 :: EU Stall */ #define glk__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen9 :: Samples Blended */ #define glk__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ #define glk__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ #define glk__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ #define glk__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen9 :: GTI Write Throughput */ #define glk__compute_basic__gti_write_throughput__read \ bdw__render_basic__gti_hdc_lookups_throughput__read /* Compute Metrics Basic Gen9 :: SLM Bytes Written */ #define glk__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ #define glk__compute_basic__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Basic Gen9 :: Samples Killed in FS */ #define glk__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen9 :: Samples Written */ #define glk__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ #define glk__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ #define glk__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ #define glk__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ #define glk__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ #define glk__render_pipe_profile__vs_bottleneck__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ #define glk__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ #define glk__render_pipe_profile__gs_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ #define glk__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ #define glk__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ #define glk__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ #define glk__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ #define glk__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ #define glk__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ #define glk__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ #define glk__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ #define glk__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ #define glk__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define glk__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ #define glk__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ #define glk__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ #define glk__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ #define glk__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ #define glk__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ #define glk__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ #define glk__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ #define glk__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ #define glk__render_pipe_profile__hs_bottleneck__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ #define glk__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ #define glk__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ #define glk__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ #define glk__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ #define glk__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ #define glk__render_pipe_profile__ds_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ #define glk__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ #define glk__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ #define glk__render_pipe_profile__ds_stall__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ #define glk__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ #define glk__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ #define glk__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ #define glk__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ #define glk__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ #define glk__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ #define glk__render_pipe_profile__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ #define glk__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ #define glk__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ #define glk__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen9 :: GPU Core Clocks */ #define glk__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: EU Active */ #define glk__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ #define glk__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__typed_atomics0__read /* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ #define glk__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: GtiRingAccesses */ #define glk__memory_reads__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ #define glk__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ #define glk__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ #define glk__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ #define glk__memory_reads__gti_l3_bank3_reads__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ #define glk__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ #define glk__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen9 :: Sampler Texels */ #define glk__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ #define glk__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ #define glk__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ #define glk__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define glk__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ #define glk__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ #define glk__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ #define glk__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ #define glk__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen9 :: SLM Bytes Read */ #define glk__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ #define glk__memory_reads__gti_l3_bank1_reads__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Reads Distribution Gen9 :: GPU Busy */ #define glk__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ #define glk__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ #define glk__memory_reads__gti_l3_bank2_reads__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Reads Distribution Gen9 :: GtiMemoryReads */ #define glk__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen9 :: Rasterized Pixels */ #define glk__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ #define glk__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ #define glk__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen9 :: Samples Written */ #define glk__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen9 :: EU Stall */ #define glk__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen9 :: Samples Blended */ #define glk__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ #define glk__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ #define glk__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ #define glk__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ #define glk__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ #define glk__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ #define glk__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen9 :: Samples Killed in FS */ #define glk__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen9 :: SLM Bytes Written */ #define glk__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen9 :: GtiL3Reads */ #define glk__memory_reads__gti_l3_reads__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ #define glk__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen9 :: GPU Core Clocks */ #define glk__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: EU Active */ #define glk__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ #define glk__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ #define glk__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: GtiRingAccesses */ #define glk__memory_writes__gti_ring_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ #define glk__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ #define glk__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ #define glk__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ #define glk__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ #define glk__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ #define glk__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen9 :: Sampler Texels */ #define glk__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ #define glk__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ #define glk__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__typed_atomics0__read /* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ #define glk__memory_writes__gti_l3_bank1_writes__read \ hsw__memory_reads__gti_memory_reads__read /* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ #define glk__memory_writes__gti_l3_bank2_writes__read \ hsw__memory_reads__llc_read_accesses__read /* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ #define glk__memory_writes__gti_l3_bank3_writes__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen9 :: GtiL3Writes */ #define glk__memory_writes__gti_l3_writes__read \ bdw__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ #define glk__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define glk__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ #define glk__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ #define glk__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ #define glk__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen9 :: SLM Bytes Read */ #define glk__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ #define glk__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ #define glk__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen9 :: GPU Busy */ #define glk__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ #define glk__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen9 :: Rasterized Pixels */ #define glk__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ #define glk__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen9 :: Samples Written */ #define glk__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen9 :: EU Stall */ #define glk__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen9 :: Samples Blended */ #define glk__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ #define glk__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ #define glk__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ #define glk__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ #define glk__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__gpu_clocks__read /* Memory Writes Distribution Gen9 :: SLM Bytes Written */ #define glk__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ #define glk__memory_writes__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Memory Writes Distribution Gen9 :: Samples Killed in FS */ #define glk__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ #define glk__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ #define glk__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: GPU Core Clocks */ #define glk__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: EU Active */ #define glk__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ #define glk__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ #define glk__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ #define glk__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ #define glk__compute_extended__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen9 :: Typed Writes 0 */ #define glk__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_writes0__read /* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ #define glk__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ #define glk__compute_extended__typed_atomics0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ #define glk__compute_extended__typed_atomics_per_cache_line__read \ hsw__compute_extended__typed_atomics_per_cache_line__read /* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ #define glk__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ #define glk__compute_extended__untyped_writes0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ #define glk__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ #define glk__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ #define glk__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ #define glk__compute_extended__untyped_writes_per_cache_line__read \ bdw__compute_extended__untyped_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ #define glk__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen9 :: Sampler Texels */ #define glk__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ #define glk__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define glk__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ #define glk__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ #define glk__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ #define glk__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen9 :: SLM Bytes Read */ #define glk__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ #define glk__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ #define glk__compute_extended__typed_writes_per_cache_line__read \ hsw__compute_extended__typed_writes_per_cache_line__read /* Compute Metrics Extended Gen9 :: Typed Reads 0 */ #define glk__compute_extended__typed_reads0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ #define glk__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ #define glk__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ #define glk__compute_extended__eu_thread_occupancy__read \ bdw__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen9 :: EU Stall */ #define glk__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen9 :: EuTypedReads0 */ #define glk__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ #define glk__compute_extended__untyped_reads_per_cache_line__read \ bdw__compute_extended__untyped_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ #define glk__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ #define glk__compute_extended__typed_reads_per_cache_line__read \ hsw__compute_extended__typed_reads_per_cache_line__read /* Compute Metrics Extended Gen9 :: SLM Bytes Written */ #define glk__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ #define glk__compute_extended__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ #define glk__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ #define glk__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ #define glk__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen9 :: EU Active */ #define glk__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ #define glk__compute_l3_cache__l3_bank03_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ #define glk__compute_l3_cache__l3_accesses__read \ sklgt2__compute_l3_cache__l3_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ #define glk__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ #define glk__compute_l3_cache__l3_sampler_throughput__read \ chv__render_basic__l3_sampler_throughput__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ #define glk__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ #define glk__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ #define glk__compute_l3_cache__eu_avg_ipc_rate__read \ bdw__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ #define glk__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ #define glk__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ #define glk__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ #define glk__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ #define glk__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ #define glk__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ #define glk__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: L3 Misses */ #define glk__compute_l3_cache__l3_misses__read \ bdw__compute_l3_cache__l3_misses__read /* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ #define glk__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ #define glk__compute_l3_cache__l3_bank00_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ #define glk__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ #define glk__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ #define glk__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ #define glk__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ #define glk__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define glk__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ #define glk__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ #define glk__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ #define glk__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ #define glk__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ #define glk__compute_l3_cache__gti_read_throughput__read \ bdw__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ #define glk__compute_l3_cache__gti_l3_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ #define glk__compute_l3_cache__l3_bank00_ic_accesses__read \ bdw__compute_l3_cache__l3_bank00_ic_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ #define glk__compute_l3_cache__l3_bank00_ic_hits__read \ bdw__compute_l3_cache__l3_bank00_ic_hits__read /* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ #define glk__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ #define glk__compute_l3_cache__l3_bank01_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen9 :: GPU Busy */ #define glk__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ #define glk__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ #define glk__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ #define glk__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ #define glk__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen9 :: Samples Written */ #define glk__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ #define glk__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen9 :: EU Stall */ #define glk__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen9 :: Samples Blended */ #define glk__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ #define glk__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ #define glk__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ #define glk__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ #define glk__compute_l3_cache__l3_total_throughput__read \ sklgt2__compute_l3_cache__l3_total_throughput__read /* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ #define glk__compute_l3_cache__gti_write_throughput__read \ hsw__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ #define glk__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ #define glk__compute_l3_cache__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ #define glk__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ #define glk__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ #define glk__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ #define glk__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define glk__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define glk__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define glk__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define glk__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define glk__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define glk__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define glk__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define glk__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define glk__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define glk__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define glk__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define glk__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define glk__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define glk__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define glk__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define glk__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define glk__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define glk__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ #define glk__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read /* Metric set HDCAndSF :: CS Threads Dispatched */ #define glk__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: SLM Bytes Read */ #define glk__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define glk__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define glk__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define glk__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define glk__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define glk__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define glk__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define glk__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define glk__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define glk__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define glk__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define glk__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define glk__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define glk__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: SLM Bytes Written */ #define glk__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define glk__hdc_and_sf__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define glk__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ #define glk__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define glk__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define glk__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define glk__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define glk__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define glk__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: VS Send Pipe Active */ #define glk__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define glk__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define glk__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define glk__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define glk__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define glk__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define glk__l3_1__l30_bank1_stalled__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set L3_1 :: FS Threads Dispatched */ #define glk__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define glk__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define glk__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define glk__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define glk__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define glk__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define glk__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define glk__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define glk__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define glk__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define glk__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define glk__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define glk__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define glk__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define glk__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define glk__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define glk__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define glk__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define glk__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define glk__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define glk__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define glk__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define glk__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define glk__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define glk__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: SLM Bytes Written */ #define glk__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: L3 Shader Throughput */ #define glk__l3_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define glk__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define glk__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define glk__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define glk__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define glk__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define glk__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define glk__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define glk__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define glk__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define glk__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define glk__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define glk__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define glk__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define glk__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define glk__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define glk__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define glk__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define glk__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define glk__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define glk__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define glk__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define glk__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define glk__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define glk__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define glk__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define glk__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define glk__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define glk__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define glk__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define glk__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define glk__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define glk__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define glk__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define glk__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define glk__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define glk__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define glk__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define glk__rasterizer_and_pixel_backend__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define glk__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define glk__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define glk__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define glk__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define glk__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define glk__sampler__sampler02_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define glk__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: VS Send Pipe Active */ #define glk__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define glk__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define glk__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define glk__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define glk__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define glk__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define glk__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define glk__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: FS Threads Dispatched */ #define glk__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define glk__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define glk__sampler__sampler01_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: Sampler Texels */ #define glk__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define glk__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define glk__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define glk__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define glk__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define glk__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define glk__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define glk__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define glk__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define glk__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define glk__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define glk__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Rasterized Pixels */ #define glk__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define glk__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define glk__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define glk__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define glk__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define glk__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define glk__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define glk__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define glk__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: Shader Memory Accesses */ #define glk__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: HS Threads Dispatched */ #define glk__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: SLM Bytes Written */ #define glk__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: L3 Shader Throughput */ #define glk__sampler__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define glk__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define glk__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define glk__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define glk__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define glk__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define glk__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define glk__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define glk__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define glk__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define glk__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define glk__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define glk__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ #define glk__tdl_1__non_ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define glk__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define glk__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define glk__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define glk__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define glk__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define glk__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define glk__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ #define glk__tdl_1__non_ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define glk__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define glk__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define glk__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define glk__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define glk__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define glk__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define glk__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define glk__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define glk__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define glk__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define glk__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define glk__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define glk__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define glk__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define glk__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define glk__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define glk__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define glk__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: SLM Bytes Written */ #define glk__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define glk__tdl_1__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define glk__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define glk__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ #define glk__tdl_1__non_ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define glk__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define glk__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define glk__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define glk__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define glk__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define glk__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define glk__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define glk__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define glk__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define glk__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define glk__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define glk__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define glk__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define glk__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define glk__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define glk__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define glk__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define glk__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define glk__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define glk__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define glk__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define glk__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define glk__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define glk__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define glk__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define glk__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define glk__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define glk__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define glk__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define glk__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define glk__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define glk__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define glk__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define glk__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define glk__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define glk__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: SLM Bytes Written */ #define glk__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define glk__tdl_2__l3_shader_throughput__read \ bdw__hdc_and_sf__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define glk__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define glk__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define glk__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define glk__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Compute Metrics Extra Gen9 :: GPU Core Clocks */ #define glk__compute_extra__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ #define glk__compute_extra__fpu1_active__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ #define glk__compute_extra__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define glk__compute_extra__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ #define glk__compute_extra__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ #define glk__compute_extra__fpu1_active_adjusted__read \ sklgt2__compute_extra__fpu1_active_adjusted__read /* MDAPI testing set Gen9 :: TestCounter7 */ #define glk__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* MDAPI testing set Gen9 :: GPU Time Elapsed */ #define glk__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* MDAPI testing set Gen9 :: GPU Core Clocks */ #define glk__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define glk__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ #define glk__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* MDAPI testing set Gen9 :: TestCounter8 */ #define glk__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* MDAPI testing set Gen9 :: TestCounter4 */ #define glk__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* MDAPI testing set Gen9 :: TestCounter5 */ #define glk__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* MDAPI testing set Gen9 :: TestCounter6 */ #define glk__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* MDAPI testing set Gen9 :: TestCounter3 */ #define glk__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* MDAPI testing set Gen9 :: TestCounter0 */ #define glk__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* MDAPI testing set Gen9 :: TestCounter1 */ #define glk__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* MDAPI testing set Gen9 :: TestCounter2 */ #define glk__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Metric set PMA Stall :: GPU Time Elapsed */ #define glk__pma__stall__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set PMA Stall :: GPU Core Clocks */ #define glk__pma__stall__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set PMA Stall :: STC PMA stall */ #define glk__pma__stall__stc_pma_stall__read \ sklgt2__pma__stall__stc_pma_stall__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define glk__pma__stall__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set PMA Stall :: AVG GPU Core Frequency */ #define glk__pma__stall__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen10 :: GPU Core Clocks */ #define cnl__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen10 :: EU Active */ #define cnl__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen10 :: L3 Misses */ static uint64_t cnl__render_basic__l3_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ C 3 READ UADD */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = accumulator[query->c_offset + 3]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* Render Metrics Basic Gen10 :: GTI L3 Throughput */ #define cnl__render_basic__gti_l3_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Render Metrics Basic Gen10 :: EU Both FPU Pipes Active */ #define cnl__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen10 :: Sampler Cache Misses */ static uint64_t cnl__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SliceMask 1 AND B 4 READ UMUL $SliceMask 1 >> 1 AND B 5 READ UMUL UADD 8 UMUL */ uint64_t tmp0 = perf->sys_vars.slice_mask & 1; uint64_t tmp1 = accumulator[query->b_offset + 4]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.slice_mask >> 1; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->b_offset + 5]; uint64_t tmp6 = tmp4 * tmp5; uint64_t tmp7 = tmp2 + tmp6; uint64_t tmp8 = tmp7 * 8; return tmp8; } /* Render Metrics Basic Gen10 :: VS Send Pipe Active */ #define cnl__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen10 :: VS FPU1 Pipe Active */ #define cnl__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen10 :: GS Threads Dispatched */ #define cnl__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen10 :: L3 Sampler Throughput */ static uint64_t cnl__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 $SamplerL1Misses UMUL */ uint64_t tmp0 = 64 * cnl__render_basic__sampler_l1_misses__read(perf, query, accumulator); return tmp0; } /* Render Metrics Basic Gen10 :: Early Hi-Depth Test Fails */ #define cnl__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen10 :: FS Both FPU Active */ #define cnl__render_basic__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Render Metrics Basic Gen10 :: VS Threads Dispatched */ #define cnl__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen10 :: FS Threads Dispatched */ #define cnl__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen10 :: Sampler00 Busy */ #define cnl__render_basic__sampler00_busy__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics Basic Gen10 :: Sampler10 Busy */ #define cnl__render_basic__sampler10_busy__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics Basic Gen10 :: Samplers Busy */ static float cnl__render_basic__samplers_busy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SubsliceMask 1 AND $Sampler00Busy FMUL $SubsliceMask 3 >> 1 AND $Sampler10Busy FMUL FADD $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV */ uint64_t tmp0 = perf->sys_vars.subslice_mask & 1; double tmp1 = tmp0 * cnl__render_basic__sampler00_busy__read(perf, query, accumulator); uint64_t tmp2 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp3 = tmp2 & 1; double tmp4 = tmp3 * cnl__render_basic__sampler10_busy__read(perf, query, accumulator); double tmp5 = tmp1 + tmp4; uint64_t tmp6 = perf->sys_vars.subslice_mask & 1; uint64_t tmp7 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp8 = tmp7 & 1; double tmp9 = tmp6 + tmp8; double tmp10 = tmp5; double tmp11 = tmp9; double tmp12 = tmp11 ? tmp10 / tmp11 : 0; return tmp12; } /* Render Metrics Basic Gen10 :: GTI Fixed Pipe Throughput */ #define cnl__render_basic__gti_vf_throughput__read \ bdw__compute_l3_cache__gti_l3_throughput__read /* Render Metrics Basic Gen10 :: Shader Barrier Messages */ #define cnl__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen10 :: Sampler Texels */ #define cnl__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen10 :: Pixels Failing Tests */ #define cnl__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen10 :: GPU Time Elapsed */ #define cnl__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen10 :: AVG GPU Core Frequency */ #define cnl__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen10 :: AVG GPU Core Frequency */ #define cnl__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen10 :: Sampler Texels Misses */ #define cnl__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen10 :: CS Threads Dispatched */ #define cnl__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen10 :: Shader Memory Accesses */ #define cnl__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen10 :: L3 Lookup Accesses w/o IC */ static uint64_t cnl__render_basic__l3_lookups__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ uint64_t tmp0 = cnl__render_basic__sampler_l1_misses__read(perf, query, accumulator) + cnl__render_basic__shader_memory_accesses__read(perf, query, accumulator); return tmp0; } /* Render Metrics Basic Gen10 :: Sampler00 Bottleneck */ #define cnl__render_basic__sampler00_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics Basic Gen10 :: SLM Bytes Read */ #define cnl__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen10 :: GTI Read Throughput */ static uint64_t cnl__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 C 6 READ UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = 64 * tmp0; return tmp1; } /* Render Metrics Basic Gen10 :: PS FPU1 Pipe Active */ #define cnl__render_basic__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Render Metrics Basic Gen10 :: PS Send Pipeline Active */ #define cnl__render_basic__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Render Metrics Basic Gen10 :: Rasterized Pixels */ #define cnl__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen10 :: GPU Busy */ #define cnl__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen10 :: GTI Depth Throughput */ static uint64_t cnl__render_basic__gti_depth_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 128 B 6 READ UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = 128 * tmp0; return tmp1; } /* Render Metrics Basic Gen10 :: VS FPU0 Pipe Active */ #define cnl__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen10 :: PS FPU0 Pipe Active */ #define cnl__render_basic__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen10 :: DS Threads Dispatched */ #define cnl__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen10 :: Samples Written */ #define cnl__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen10 :: EU Stall */ #define cnl__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen10 :: Samples Blended */ #define cnl__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen10 :: Early Depth Test Fails */ #define cnl__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen10 :: Sampler10 Bottleneck */ #define cnl__render_basic__sampler10_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics Basic Gen10 :: Samplers Bottleneck */ static float cnl__render_basic__sampler_bottleneck__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SubsliceMask 1 AND $Sampler00Bottleneck FMUL $SubsliceMask 3 >> 1 AND $Sampler10Bottleneck FMUL FADD $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV */ uint64_t tmp0 = perf->sys_vars.subslice_mask & 1; double tmp1 = tmp0 * cnl__render_basic__sampler00_bottleneck__read(perf, query, accumulator); uint64_t tmp2 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp3 = tmp2 & 1; double tmp4 = tmp3 * cnl__render_basic__sampler10_bottleneck__read(perf, query, accumulator); double tmp5 = tmp1 + tmp4; uint64_t tmp6 = perf->sys_vars.subslice_mask & 1; uint64_t tmp7 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp8 = tmp7 & 1; double tmp9 = tmp6 + tmp8; double tmp10 = tmp5; double tmp11 = tmp9; double tmp12 = tmp11 ? tmp10 / tmp11 : 0; return tmp12; } /* Render Metrics Basic Gen10 :: GTI RCC Throughput */ static uint64_t cnl__render_basic__gti_rcc_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ C 1 READ UADD 128 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 128; return tmp3; } /* Render Metrics Basic Gen10 :: HS Threads Dispatched */ #define cnl__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen10 :: GTI Write Throughput */ static uint64_t cnl__render_basic__gti_write_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 C 7 READ UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = 64 * tmp0; return tmp1; } /* Render Metrics Basic Gen10 :: L3 Shader Throughput */ static uint64_t cnl__render_basic__l3_shader_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 30 READ A 31 READ UADD A 32 READ UADD 64 UMUL */ uint64_t tmp0 = accumulator[query->a_offset + 30]; uint64_t tmp1 = accumulator[query->a_offset + 31]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->a_offset + 32]; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = tmp4 * 64; return tmp5; } /* Render Metrics Basic Gen10 :: Samples Killed in FS */ #define cnl__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen10 :: SLM Bytes Written */ #define cnl__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen10 :: Shader Atomic Memory Accesses */ #define cnl__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen10 :: GPU Core Clocks */ #define cnl__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen10 :: EU Active */ #define cnl__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen10 :: Untyped Bytes Read */ static uint64_t cnl__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuSubslicesTotalCount $SubsliceMask 1 AND C 2 READ FMUL $SubsliceMask 3 >> 1 AND C 3 READ FMUL FADD FMUL $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV 64 UMUL */ uint64_t tmp0 = perf->sys_vars.subslice_mask & 1; uint64_t tmp1 = accumulator[query->c_offset + 2]; double tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->c_offset + 3]; double tmp6 = tmp4 * tmp5; double tmp7 = tmp2 + tmp6; double tmp8 = perf->sys_vars.n_eu_sub_slices * tmp7; uint64_t tmp9 = perf->sys_vars.subslice_mask & 1; uint64_t tmp10 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp11 = tmp10 & 1; double tmp12 = tmp9 + tmp11; double tmp13 = tmp8; double tmp14 = tmp12; double tmp15 = tmp14 ? tmp13 / tmp14 : 0; uint64_t tmp16 = tmp15 * 64; return tmp16; } /* Compute Metrics Basic Gen10 :: EU Both FPU Pipes Active */ #define cnl__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen10 :: Typed Bytes Written */ static uint64_t cnl__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SubsliceMask 1 AND B 5 READ UMUL $SubsliceMask 1 >> 1 AND B 6 READ UMUL UADD $SubsliceMask 2 >> 1 AND B 7 READ UMUL UADD $SubsliceMask 3 >> 1 AND C 0 READ UMUL UADD $SubsliceMask 4 >> 1 AND C 1 READ UMUL UADD 64 UMUL */ uint64_t tmp0 = perf->sys_vars.subslice_mask & 1; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.subslice_mask >> 1; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->b_offset + 6]; uint64_t tmp6 = tmp4 * tmp5; uint64_t tmp7 = tmp2 + tmp6; uint64_t tmp8 = perf->sys_vars.subslice_mask >> 2; uint64_t tmp9 = tmp8 & 1; uint64_t tmp10 = accumulator[query->b_offset + 7]; uint64_t tmp11 = tmp9 * tmp10; uint64_t tmp12 = tmp7 + tmp11; uint64_t tmp13 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp14 = tmp13 & 1; uint64_t tmp15 = accumulator[query->c_offset + 0]; uint64_t tmp16 = tmp14 * tmp15; uint64_t tmp17 = tmp12 + tmp16; uint64_t tmp18 = perf->sys_vars.subslice_mask >> 4; uint64_t tmp19 = tmp18 & 1; uint64_t tmp20 = accumulator[query->c_offset + 1]; uint64_t tmp21 = tmp19 * tmp20; uint64_t tmp22 = tmp17 + tmp21; uint64_t tmp23 = tmp22 * 64; return tmp23; } /* Compute Metrics Basic Gen10 :: EU AVG IPC Rate */ static float cnl__compute_basic__eu_avg_ipc_rate__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 9 READ A 10 READ A 11 READ FADD A 9 READ FSUB FDIV 1 FADD */ uint64_t tmp0 = accumulator[query->a_offset + 9]; uint64_t tmp1 = accumulator[query->a_offset + 10]; uint64_t tmp2 = accumulator[query->a_offset + 11]; double tmp3 = tmp1 + tmp2; uint64_t tmp4 = accumulator[query->a_offset + 9]; double tmp5 = tmp3 - tmp4; double tmp6 = tmp0; double tmp7 = tmp5; double tmp8 = tmp7 ? tmp6 / tmp7 : 0; double tmp9 = tmp8 + 1; return tmp9; } /* Compute Metrics Basic Gen10 :: GS Threads Dispatched */ #define cnl__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen10 :: Early Hi-Depth Test Fails */ #define cnl__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen10 :: VS Threads Dispatched */ #define cnl__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen10 :: FS Threads Dispatched */ #define cnl__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen10 :: EU FPU1 Pipe Active */ #define cnl__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen10 :: EU FPU0 Pipe Active */ #define cnl__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen10 :: Shader Barrier Messages */ #define cnl__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen10 :: Sampler Texels */ #define cnl__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen10 :: Pixels Failing Tests */ #define cnl__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen10 :: GPU Time Elapsed */ #define cnl__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen10 :: AVG GPU Core Frequency */ #define cnl__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen10 :: AVG GPU Core Frequency */ #define cnl__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen10 :: Sampler Texels Misses */ #define cnl__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen10 :: CS Threads Dispatched */ #define cnl__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen10 :: SLM Bytes Read */ #define cnl__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen10 :: GTI Read Throughput */ #define cnl__compute_basic__gti_read_throughput__read \ cnl__render_basic__gti_read_throughput__read /* Compute Metrics Basic Gen10 :: Untyped Writes */ static uint64_t cnl__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuSubslicesTotalCount $SubsliceMask 1 AND C 4 READ FMUL $SubsliceMask 3 >> 1 AND C 5 READ FMUL FADD FMUL $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV 64 UMUL */ uint64_t tmp0 = perf->sys_vars.subslice_mask & 1; uint64_t tmp1 = accumulator[query->c_offset + 4]; double tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->c_offset + 5]; double tmp6 = tmp4 * tmp5; double tmp7 = tmp2 + tmp6; double tmp8 = perf->sys_vars.n_eu_sub_slices * tmp7; uint64_t tmp9 = perf->sys_vars.subslice_mask & 1; uint64_t tmp10 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp11 = tmp10 & 1; double tmp12 = tmp9 + tmp11; double tmp13 = tmp8; double tmp14 = tmp12; double tmp15 = tmp14 ? tmp13 / tmp14 : 0; uint64_t tmp16 = tmp15 * 64; return tmp16; } /* Compute Metrics Basic Gen10 :: GPU Busy */ #define cnl__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen10 :: Rasterized Pixels */ #define cnl__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen10 :: Typed Bytes Read */ static uint64_t cnl__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SubsliceMask 1 AND B 0 READ UMUL $SubsliceMask 1 >> 1 AND B 1 READ UMUL UADD $SubsliceMask 2 >> 1 AND B 2 READ UMUL UADD $SubsliceMask 3 >> 1 AND B 3 READ UMUL UADD $SubsliceMask 4 >> 1 AND B 4 READ UMUL UADD 64 UMUL */ uint64_t tmp0 = perf->sys_vars.subslice_mask & 1; uint64_t tmp1 = accumulator[query->b_offset + 0]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.subslice_mask >> 1; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->b_offset + 1]; uint64_t tmp6 = tmp4 * tmp5; uint64_t tmp7 = tmp2 + tmp6; uint64_t tmp8 = perf->sys_vars.subslice_mask >> 2; uint64_t tmp9 = tmp8 & 1; uint64_t tmp10 = accumulator[query->b_offset + 2]; uint64_t tmp11 = tmp9 * tmp10; uint64_t tmp12 = tmp7 + tmp11; uint64_t tmp13 = perf->sys_vars.subslice_mask >> 3; uint64_t tmp14 = tmp13 & 1; uint64_t tmp15 = accumulator[query->b_offset + 3]; uint64_t tmp16 = tmp14 * tmp15; uint64_t tmp17 = tmp12 + tmp16; uint64_t tmp18 = perf->sys_vars.subslice_mask >> 4; uint64_t tmp19 = tmp18 & 1; uint64_t tmp20 = accumulator[query->b_offset + 4]; uint64_t tmp21 = tmp19 * tmp20; uint64_t tmp22 = tmp17 + tmp21; uint64_t tmp23 = tmp22 * 64; return tmp23; } /* Compute Metrics Basic Gen10 :: DS Threads Dispatched */ #define cnl__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen10 :: EU Thread Occupancy */ static float cnl__compute_basic__eu_thread_occupancy__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 8 A 13 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; double tmp1 = 8 * tmp0; double tmp2 = tmp1; double tmp3 = perf->sys_vars.eu_threads_count; double tmp4 = tmp3 ? tmp2 / tmp3 : 0; uint64_t tmp5 = tmp4; uint64_t tmp6 = perf->sys_vars.n_eus; uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0; uint64_t tmp8 = tmp7 * 100; double tmp9 = tmp8; double tmp10 = cnl__compute_basic__gpu_core_clocks__read(perf, query, accumulator); double tmp11 = tmp10 ? tmp9 / tmp10 : 0; return tmp11; } /* Compute Metrics Basic Gen10 :: EU Stall */ #define cnl__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen10 :: Samples Blended */ #define cnl__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen10 :: Early Depth Test Fails */ #define cnl__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen10 :: Shader Memory Accesses */ #define cnl__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen10 :: HS Threads Dispatched */ #define cnl__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen10 :: GTI Write Throughput */ #define cnl__compute_basic__gti_write_throughput__read \ cnl__render_basic__gti_write_throughput__read /* Compute Metrics Basic Gen10 :: L3 Shader Throughput */ #define cnl__compute_basic__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Compute Metrics Basic Gen10 :: Samples Killed in FS */ #define cnl__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen10 :: SLM Bytes Written */ #define cnl__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen10 :: Samples Written */ #define cnl__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen10 :: Shader Atomic Memory Accesses */ #define cnl__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen10 :: EU Send Pipe Active */ #define cnl__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen10 :: GPU Core Clocks */ #define cnl__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen10 :: EU Active */ #define cnl__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen10 :: VS Bottleneck */ #define cnl__render_pipe_profile__vs_bottleneck__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Hi-Depth Bottleneck */ #define cnl__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: GS Bottleneck */ #define cnl__render_pipe_profile__gs_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: GS Threads Dispatched */ #define cnl__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Early Hi-Depth Test Fails */ #define cnl__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen10 :: VS Threads Dispatched */ #define cnl__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen10 :: FS Threads Dispatched */ #define cnl__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen10 :: BC Bottleneck */ #define cnl__render_pipe_profile__bc_bottleneck__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: HS Stall */ #define cnl__render_pipe_profile__hs_stall__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Shader Barrier Messages */ #define cnl__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Sampler Texels */ #define cnl__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Pixels Failing Tests */ #define cnl__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen10 :: GPU Time Elapsed */ #define cnl__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen10 :: AVG GPU Core Frequency */ #define cnl__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen10 :: AVG GPU Core Frequency */ #define cnl__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen10 :: Sampler Texels Misses */ #define cnl__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen10 :: CS Threads Dispatched */ #define cnl__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen10 :: VF Bottleneck */ #define cnl__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: SLM Bytes Read */ #define cnl__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Strip-Fans Bottleneck */ #define cnl__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: SF Stall */ #define cnl__render_pipe_profile__sf_stall__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen10 :: GPU Busy */ #define cnl__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen10 :: HS Bottleneck */ #define cnl__render_pipe_profile__hs_bottleneck__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen10 :: CL Stall */ #define cnl__render_pipe_profile__cl_stall__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen10 :: SO Bottleneck */ #define cnl__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Rasterized Pixels */ #define cnl__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen10 :: DS Threads Dispatched */ #define cnl__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Samples Written */ #define cnl__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen10 :: DS Bottleneck */ #define cnl__render_pipe_profile__ds_bottleneck__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen10 :: EU Stall */ #define cnl__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Clipper Bottleneck */ #define cnl__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: DS Stall */ #define cnl__render_pipe_profile__ds_stall__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Early Depth Bottleneck */ #define cnl__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Samples Blended */ #define cnl__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Early Depth Test Fails */ #define cnl__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Shader Memory Accesses */ #define cnl__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen10 :: HS Threads Dispatched */ #define cnl__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen10 :: L3 Shader Throughput */ #define cnl__render_pipe_profile__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Samples Killed in FS */ #define cnl__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen10 :: SLM Bytes Written */ #define cnl__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen10 :: SO Stall */ #define cnl__render_pipe_profile__so_stall__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen10 :: Shader Atomic Memory Accesses */ #define cnl__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Reads Distribution Gen10 :: GPU Core Clocks */ #define cnl__memory_reads__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen10 :: EU Active */ #define cnl__memory_reads__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Reads Distribution Gen10 :: GtiL3Bank0Reads */ #define cnl__memory_reads__gti_l3_bank0_reads__read \ hsw__compute_extended__untyped_writes0__read /* Memory Reads Distribution Gen10 :: GS Threads Dispatched */ #define cnl__memory_reads__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Reads Distribution Gen10 :: GtiRingAccesses */ #define cnl__memory_reads__gti_ring_accesses__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Reads Distribution Gen10 :: Early Hi-Depth Test Fails */ #define cnl__memory_reads__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Reads Distribution Gen10 :: VS Threads Dispatched */ #define cnl__memory_reads__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Reads Distribution Gen10 :: FS Threads Dispatched */ #define cnl__memory_reads__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Reads Distribution Gen10 :: Shader Barrier Messages */ #define cnl__memory_reads__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen10 :: GtiRsMemoryReads */ #define cnl__memory_reads__gti_rs_memory_reads__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Reads Distribution Gen10 :: Sampler Texels */ #define cnl__memory_reads__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Reads Distribution Gen10 :: Pixels Failing Tests */ #define cnl__memory_reads__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Reads Distribution Gen10 :: GtiHizMemoryReads */ #define cnl__memory_reads__gti_hiz_memory_reads__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Reads Distribution Gen10 :: GPU Time Elapsed */ #define cnl__memory_reads__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Reads Distribution Gen10 :: AVG GPU Core Frequency */ #define cnl__memory_reads__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Reads Distribution Gen10 :: AVG GPU Core Frequency */ #define cnl__memory_reads__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Reads Distribution Gen10 :: Sampler Texels Misses */ #define cnl__memory_reads__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Reads Distribution Gen10 :: GtiRccMemoryReads */ #define cnl__memory_reads__gti_rcc_memory_reads__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Reads Distribution Gen10 :: CS Threads Dispatched */ #define cnl__memory_reads__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Reads Distribution Gen10 :: SLM Bytes Read */ #define cnl__memory_reads__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Reads Distribution Gen10 :: GtiL3Bank1Reads */ #define cnl__memory_reads__gti_l3_bank1_reads__read \ hsw__render_basic__gpu_core_clocks__read /* Memory Reads Distribution Gen10 :: GPU Busy */ #define cnl__memory_reads__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Reads Distribution Gen10 :: GtiCmdStreamerMemoryReads */ #define cnl__memory_reads__gti_cmd_streamer_memory_reads__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Reads Distribution Gen10 :: GtiL3Bank2Reads */ #define cnl__memory_reads__gti_l3_bank2_reads__read \ hsw__compute_extended__untyped_reads0__read /* Memory Reads Distribution Gen10 :: GtiMemoryReads */ #define cnl__memory_reads__gti_memory_reads__read \ hsw__compute_extended__typed_writes0__read /* Memory Reads Distribution Gen10 :: Rasterized Pixels */ #define cnl__memory_reads__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Reads Distribution Gen10 :: GtiRczMemoryReads */ #define cnl__memory_reads__gti_rcz_memory_reads__read \ hsw__compute_extended__gpu_clocks__read /* Memory Reads Distribution Gen10 :: DS Threads Dispatched */ #define cnl__memory_reads__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Reads Distribution Gen10 :: Samples Written */ #define cnl__memory_reads__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Reads Distribution Gen10 :: EU Stall */ #define cnl__memory_reads__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Reads Distribution Gen10 :: Samples Blended */ #define cnl__memory_reads__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Reads Distribution Gen10 :: Early Depth Test Fails */ #define cnl__memory_reads__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Reads Distribution Gen10 :: GtiMscMemoryReads */ #define cnl__memory_reads__gti_msc_memory_reads__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Reads Distribution Gen10 :: GtiVfMemoryReads */ #define cnl__memory_reads__gti_vf_memory_reads__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Reads Distribution Gen10 :: GtiStcMemoryReads */ #define cnl__memory_reads__gti_stc_memory_reads__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Reads Distribution Gen10 :: Shader Memory Accesses */ #define cnl__memory_reads__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Reads Distribution Gen10 :: HS Threads Dispatched */ #define cnl__memory_reads__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Reads Distribution Gen10 :: Samples Killed in FS */ #define cnl__memory_reads__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Reads Distribution Gen10 :: SLM Bytes Written */ #define cnl__memory_reads__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Reads Distribution Gen10 :: GtiL3Reads */ static uint64_t cnl__memory_reads__gti_l3_reads__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $GtiL3Bank0Reads $GtiL3Bank1Reads UADD $GtiL3Bank2Reads UADD */ uint64_t tmp0 = cnl__memory_reads__gti_l3_bank0_reads__read(perf, query, accumulator) + cnl__memory_reads__gti_l3_bank1_reads__read(perf, query, accumulator); uint64_t tmp1 = tmp0 + cnl__memory_reads__gti_l3_bank2_reads__read(perf, query, accumulator); return tmp1; } /* Memory Reads Distribution Gen10 :: Shader Atomic Memory Accesses */ #define cnl__memory_reads__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Memory Writes Distribution Gen10 :: GPU Core Clocks */ #define cnl__memory_writes__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen10 :: EU Active */ #define cnl__memory_writes__eu_active__read \ bdw__render_basic__eu_active__read /* Memory Writes Distribution Gen10 :: GtiMemoryWrites */ #define cnl__memory_writes__gti_memory_writes__read \ hsw__compute_extended__typed_writes0__read /* Memory Writes Distribution Gen10 :: GS Threads Dispatched */ #define cnl__memory_writes__gs_threads__read \ hsw__render_basic__vs_threads__read /* Memory Writes Distribution Gen10 :: GtiRingAccesses */ #define cnl__memory_writes__gti_ring_accesses__read \ hsw__memory_reads__gpu_core_clocks__read /* Memory Writes Distribution Gen10 :: Early Hi-Depth Test Fails */ #define cnl__memory_writes__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Memory Writes Distribution Gen10 :: VS Threads Dispatched */ #define cnl__memory_writes__vs_threads__read \ bdw__render_basic__vs_threads__read /* Memory Writes Distribution Gen10 :: FS Threads Dispatched */ #define cnl__memory_writes__ps_threads__read \ bdw__render_basic__ps_threads__read /* Memory Writes Distribution Gen10 :: GtiMscMemoryWrites */ #define cnl__memory_writes__gti_msc_memory_writes__read \ hsw__compute_extended__eu_typed_writes0__read /* Memory Writes Distribution Gen10 :: Shader Barrier Messages */ #define cnl__memory_writes__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen10 :: GtiCmdStreamerMemoryWrites */ #define cnl__memory_writes__gti_cmd_streamer_memory_writes__read \ hsw__compute_extended__eu_untyped_reads0__read /* Memory Writes Distribution Gen10 :: Sampler Texels */ #define cnl__memory_writes__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Memory Writes Distribution Gen10 :: Pixels Failing Tests */ #define cnl__memory_writes__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Memory Writes Distribution Gen10 :: GtiL3Bank0Writes */ #define cnl__memory_writes__gti_l3_bank0_writes__read \ hsw__compute_extended__untyped_writes0__read /* Memory Writes Distribution Gen10 :: GtiL3Bank1Writes */ #define cnl__memory_writes__gti_l3_bank1_writes__read \ hsw__render_basic__gpu_core_clocks__read /* Memory Writes Distribution Gen10 :: GtiL3Bank2Writes */ #define cnl__memory_writes__gti_l3_bank2_writes__read \ hsw__compute_extended__untyped_reads0__read /* Memory Writes Distribution Gen10 :: GtiL3Writes */ #define cnl__memory_writes__gti_l3_writes__read \ cnl__memory_reads__gti_l3_reads__read /* Memory Writes Distribution Gen10 :: GPU Time Elapsed */ #define cnl__memory_writes__gpu_time__read \ hsw__render_basic__gpu_time__read /* Memory Writes Distribution Gen10 :: AVG GPU Core Frequency */ #define cnl__memory_writes__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Memory Writes Distribution Gen10 :: AVG GPU Core Frequency */ #define cnl__memory_writes__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Memory Writes Distribution Gen10 :: Sampler Texels Misses */ #define cnl__memory_writes__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Memory Writes Distribution Gen10 :: CS Threads Dispatched */ #define cnl__memory_writes__cs_threads__read \ bdw__render_basic__cs_threads__read /* Memory Writes Distribution Gen10 :: SLM Bytes Read */ #define cnl__memory_writes__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Memory Writes Distribution Gen10 :: GtiRccMemoryWrites */ #define cnl__memory_writes__gti_rcc_memory_writes__read \ hsw__compute_extended__eu_typed_reads0__read /* Memory Writes Distribution Gen10 :: GtiSoMemoryWrites */ #define cnl__memory_writes__gti_so_memory_writes__read \ hsw__compute_extended__eu_untyped_writes0__read /* Memory Writes Distribution Gen10 :: GPU Busy */ #define cnl__memory_writes__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Memory Writes Distribution Gen10 :: GtiStcMemoryWrites */ #define cnl__memory_writes__gti_stc_memory_writes__read \ hsw__compute_extended__eu_typed_atomics0__read /* Memory Writes Distribution Gen10 :: Rasterized Pixels */ #define cnl__memory_writes__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Memory Writes Distribution Gen10 :: DS Threads Dispatched */ #define cnl__memory_writes__ds_threads__read \ bdw__render_basic__ds_threads__read /* Memory Writes Distribution Gen10 :: Samples Written */ #define cnl__memory_writes__samples_written__read \ bdw__render_basic__samples_written__read /* Memory Writes Distribution Gen10 :: EU Stall */ #define cnl__memory_writes__eu_stall__read \ bdw__render_basic__eu_stall__read /* Memory Writes Distribution Gen10 :: Samples Blended */ #define cnl__memory_writes__samples_blended__read \ bdw__render_basic__samples_blended__read /* Memory Writes Distribution Gen10 :: Early Depth Test Fails */ #define cnl__memory_writes__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Memory Writes Distribution Gen10 :: Shader Memory Accesses */ #define cnl__memory_writes__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Memory Writes Distribution Gen10 :: HS Threads Dispatched */ #define cnl__memory_writes__hs_threads__read \ bdw__render_basic__hs_threads__read /* Memory Writes Distribution Gen10 :: GtiRczMemoryWrites */ #define cnl__memory_writes__gti_rcz_memory_writes__read \ hsw__compute_extended__eu_urb_atomics0__read /* Memory Writes Distribution Gen10 :: L3 Shader Throughput */ #define cnl__memory_writes__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Memory Writes Distribution Gen10 :: Samples Killed in FS */ #define cnl__memory_writes__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Memory Writes Distribution Gen10 :: SLM Bytes Written */ #define cnl__memory_writes__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Memory Writes Distribution Gen10 :: GtiHizMemoryWrites */ #define cnl__memory_writes__gti_hiz_memory_writes__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Memory Writes Distribution Gen10 :: Shader Atomic Memory Accesses */ #define cnl__memory_writes__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen10 :: GPU Core Clocks */ #define cnl__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen10 :: EU Active */ #define cnl__compute_extended__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Extended Gen10 :: EU Both FPU Pipes Active */ #define cnl__compute_extended__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Extended Gen10 :: EU AVG IPC Rate */ #define cnl__compute_extended__eu_avg_ipc_rate__read \ cnl__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Extended Gen10 :: Typed Writes 0 */ #define cnl__compute_extended__typed_writes0__read \ hsw__compute_extended__typed_atomics0__read /* Compute Metrics Extended Gen10 :: EuTypedAtomics0 */ #define cnl__compute_extended__eu_typed_atomics0__read \ hsw__compute_extended__gpu_clocks__read /* Compute Metrics Extended Gen10 :: Typed Atomics 0 */ #define cnl__compute_extended__typed_atomics0__read \ hsw__memory_reads__gti_memory_reads__read /* Compute Metrics Extended Gen10 :: TypedAtomicsPerCacheLine */ static float cnl__compute_extended__typed_atomics_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedAtomics0 $TypedAtomics0 FDIV */ double tmp0 = cnl__compute_extended__eu_typed_atomics0__read(perf, query, accumulator); double tmp1 = cnl__compute_extended__typed_atomics0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen10 :: EuUntypedReads0 */ #define cnl__compute_extended__eu_untyped_reads0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics Extended Gen10 :: Untyped Writes 0 */ #define cnl__compute_extended__untyped_writes0__read \ hsw__render_basic__gpu_core_clocks__read /* Compute Metrics Extended Gen10 :: EU FPU1 Pipe Active */ #define cnl__compute_extended__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Extended Gen10 :: EU FPU0 Pipe Active */ #define cnl__compute_extended__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Extended Gen10 :: EuUntypedAtomics0 */ #define cnl__compute_extended__eu_untyped_atomics0__read \ hsw__compute_extended__eu_typed_reads0__read /* Compute Metrics Extended Gen10 :: EuUntypedWrites0 */ #define cnl__compute_extended__eu_untyped_writes0__read \ hsw__compute_extended__eu_untyped_writes0__read /* Compute Metrics Extended Gen10 :: EuA64UntypedWrites0 */ #define cnl__compute_extended__eu_a64_untyped_writes0__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Compute Metrics Extended Gen10 :: UntypedWritesPerCacheLine */ static float cnl__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuUntypedWrites0 $EuA64UntypedWrites0 FADD $UntypedWrites0 FDIV */ double tmp0 = cnl__compute_extended__eu_untyped_writes0__read(perf, query, accumulator) + cnl__compute_extended__eu_a64_untyped_writes0__read(perf, query, accumulator); double tmp1 = tmp0; double tmp2 = cnl__compute_extended__untyped_writes0__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Compute Metrics Extended Gen10 :: Shader Barrier Messages */ #define cnl__compute_extended__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Extended Gen10 :: Sampler Texels */ #define cnl__compute_extended__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Extended Gen10 :: GPU Time Elapsed */ #define cnl__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Extended Gen10 :: AVG GPU Core Frequency */ #define cnl__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Extended Gen10 :: AVG GPU Core Frequency */ #define cnl__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Extended Gen10 :: Sampler Texels Misses */ #define cnl__compute_extended__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Extended Gen10 :: CS Threads Dispatched */ #define cnl__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Extended Gen10 :: SLM Bytes Read */ #define cnl__compute_extended__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Extended Gen10 :: EuTypedWrites0 */ #define cnl__compute_extended__eu_typed_writes0__read \ hsw__compute_extended__eu_urb_atomics0__read /* Compute Metrics Extended Gen10 :: TypedWritesPerCacheLine */ static float cnl__compute_extended__typed_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedWrites0 $TypedWrites0 FDIV */ double tmp0 = cnl__compute_extended__eu_typed_writes0__read(perf, query, accumulator); double tmp1 = cnl__compute_extended__typed_writes0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen10 :: Typed Reads 0 */ #define cnl__compute_extended__typed_reads0__read \ hsw__compute_extended__untyped_reads0__read /* Compute Metrics Extended Gen10 :: Untyped Reads 0 */ #define cnl__compute_extended__untyped_reads0__read \ hsw__compute_extended__untyped_writes0__read /* Compute Metrics Extended Gen10 :: EuA64UntypedReads0 */ #define cnl__compute_extended__eu_a64_untyped_reads0__read \ hsw__compute_extended__eu_typed_writes0__read /* Compute Metrics Extended Gen10 :: EU Thread Occupancy */ #define cnl__compute_extended__eu_thread_occupancy__read \ cnl__compute_basic__eu_thread_occupancy__read /* Compute Metrics Extended Gen10 :: EU Stall */ #define cnl__compute_extended__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Extended Gen10 :: EuTypedReads0 */ #define cnl__compute_extended__eu_typed_reads0__read \ hsw__compute_extended__eu_typed_atomics0__read /* Compute Metrics Extended Gen10 :: UntypedReadsPerCacheLine */ static float cnl__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuUntypedReads0 $EuA64UntypedReads0 FADD $UntypedReads0 FDIV */ double tmp0 = cnl__compute_extended__eu_untyped_reads0__read(perf, query, accumulator) + cnl__compute_extended__eu_a64_untyped_reads0__read(perf, query, accumulator); double tmp1 = tmp0; double tmp2 = cnl__compute_extended__untyped_reads0__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; return tmp3; } /* Compute Metrics Extended Gen10 :: Shader Memory Accesses */ #define cnl__compute_extended__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Extended Gen10 :: TypedReadsPerCacheLine */ static float cnl__compute_extended__typed_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedReads0 $TypedReads0 FDIV */ double tmp0 = cnl__compute_extended__eu_typed_reads0__read(perf, query, accumulator); double tmp1 = cnl__compute_extended__typed_reads0__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* Compute Metrics Extended Gen10 :: L3 Shader Throughput */ #define cnl__compute_extended__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Compute Metrics Extended Gen10 :: SLM Bytes Written */ #define cnl__compute_extended__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Extended Gen10 :: Shader Atomic Memory Accesses */ #define cnl__compute_extended__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Extended Gen10 :: EU Send Pipe Active */ #define cnl__compute_extended__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Compute Metrics L3 Cache Gen10 :: GPU Core Clocks */ #define cnl__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen10 :: EU Active */ #define cnl__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen10 :: L3 Misses */ #define cnl__compute_l3_cache__l3_misses__read \ cnl__render_basic__l3_misses__read /* Compute Metrics L3 Cache Gen10 :: GTI L3 Throughput */ #define cnl__compute_l3_cache__gti_l3_throughput__read \ bdw__render_basic__gti_rcc_throughput__read /* Compute Metrics L3 Cache Gen10 :: Slice0 L3 Bank0 Accesses */ static uint64_t cnl__compute_l3_cache__l3_bank00_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen10 :: Slice0 L3 Bank1 Accesses */ static uint64_t cnl__compute_l3_cache__l3_bank01_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 1 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen10 :: Slice0 L3 Bank2 Accesses */ #define cnl__compute_l3_cache__l3_bank02_accesses__read \ bdw__compute_l3_cache__l3_bank02_accesses__read /* Compute Metrics L3 Cache Gen10 :: Slice1 L3 Bank0 Accesses */ #define cnl__compute_l3_cache__l3_bank10_accesses__read \ bdw__compute_l3_cache__l3_bank03_accesses__read /* Compute Metrics L3 Cache Gen10 :: Slice1 L3 Bank1 Accesses */ static uint64_t cnl__compute_l3_cache__l3_bank11_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen10 :: Slice1 L3 Bank2 Accesses */ static uint64_t cnl__compute_l3_cache__l3_bank12_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen10 :: L3 Accesses */ static uint64_t cnl__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Bank00Accesses $L3Bank01Accesses UADD $L3Bank02Accesses UADD $L3Bank10Accesses UADD $L3Bank11Accesses UADD $L3Bank12Accesses UADD */ uint64_t tmp0 = cnl__compute_l3_cache__l3_bank00_accesses__read(perf, query, accumulator) + cnl__compute_l3_cache__l3_bank01_accesses__read(perf, query, accumulator); uint64_t tmp1 = tmp0 + cnl__compute_l3_cache__l3_bank02_accesses__read(perf, query, accumulator); uint64_t tmp2 = tmp1 + cnl__compute_l3_cache__l3_bank10_accesses__read(perf, query, accumulator); uint64_t tmp3 = tmp2 + cnl__compute_l3_cache__l3_bank11_accesses__read(perf, query, accumulator); uint64_t tmp4 = tmp3 + cnl__compute_l3_cache__l3_bank12_accesses__read(perf, query, accumulator); return tmp4; } /* Compute Metrics L3 Cache Gen10 :: EU Both FPU Pipes Active */ #define cnl__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen10 :: L3 Sampler Throughput */ static uint64_t cnl__compute_l3_cache__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 $SliceMask 1 AND C 4 READ UMUL $SliceMask 1 >> 1 AND C 5 READ UMUL UADD 8 UMUL UMUL */ uint64_t tmp0 = perf->sys_vars.slice_mask & 1; uint64_t tmp1 = accumulator[query->c_offset + 4]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.slice_mask >> 1; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->c_offset + 5]; uint64_t tmp6 = tmp4 * tmp5; uint64_t tmp7 = tmp2 + tmp6; uint64_t tmp8 = tmp7 * 8; uint64_t tmp9 = 64 * tmp8; return tmp9; } /* Compute Metrics L3 Cache Gen10 :: EU AVG IPC Rate */ #define cnl__compute_l3_cache__eu_avg_ipc_rate__read \ cnl__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen10 :: EU FPU0 Binary Instruction */ #define cnl__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen10 :: GS Threads Dispatched */ #define cnl__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen10 :: Early Hi-Depth Test Fails */ #define cnl__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen10 :: VS Threads Dispatched */ #define cnl__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen10 :: FS Threads Dispatched */ #define cnl__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen10 :: EU FPU0 Hybrid Instruction */ #define cnl__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen10 :: EU FPU1 Pipe Active */ #define cnl__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen10 :: EU FPU0 Pipe Active */ #define cnl__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen10 :: Shader Barrier Messages */ #define cnl__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen10 :: EU FPU0 Move Instruction */ #define cnl__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen10 :: Sampler Accesses */ #define cnl__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen10 :: Sampler Texels */ #define cnl__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen10 :: Pixels Failing Tests */ #define cnl__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen10 :: EU FPU1 Hybrid Instruction */ #define cnl__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen10 :: GPU Time Elapsed */ #define cnl__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen10 :: AVG GPU Core Frequency */ #define cnl__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen10 :: AVG GPU Core Frequency */ #define cnl__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen10 :: Sampler Texels Misses */ #define cnl__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen10 :: CS Threads Dispatched */ #define cnl__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen10 :: L3 Lookup Accesses w/o IC */ static uint64_t cnl__compute_l3_cache__l3_lookups__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $SliceMask 1 AND C 4 READ UMUL $SliceMask 1 >> 1 AND C 5 READ UMUL UADD 8 UMUL A 32 READ UADD */ uint64_t tmp0 = perf->sys_vars.slice_mask & 1; uint64_t tmp1 = accumulator[query->c_offset + 4]; uint64_t tmp2 = tmp0 * tmp1; uint64_t tmp3 = perf->sys_vars.slice_mask >> 1; uint64_t tmp4 = tmp3 & 1; uint64_t tmp5 = accumulator[query->c_offset + 5]; uint64_t tmp6 = tmp4 * tmp5; uint64_t tmp7 = tmp2 + tmp6; uint64_t tmp8 = tmp7 * 8; uint64_t tmp9 = accumulator[query->a_offset + 32]; uint64_t tmp10 = tmp8 + tmp9; return tmp10; } /* Compute Metrics L3 Cache Gen10 :: SLM Bytes Read */ #define cnl__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen10 :: GTI Read Throughput */ #define cnl__compute_l3_cache__gti_read_throughput__read \ cnl__render_basic__gti_read_throughput__read /* Compute Metrics L3 Cache Gen10 :: GPU Busy */ #define cnl__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen10 :: EU FPU0 Ternary Instruction */ #define cnl__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen10 :: Shader Atomic Memory Accesses */ #define cnl__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen10 :: Rasterized Pixels */ #define cnl__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen10 :: DS Threads Dispatched */ #define cnl__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen10 :: Samples Written */ #define cnl__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen10 :: EU FPU1 Move Instruction */ #define cnl__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen10 :: EU Stall */ #define cnl__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen10 :: Samples Blended */ #define cnl__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen10 :: Early Depth Test Fails */ #define cnl__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen10 :: Shader Memory Accesses */ #define cnl__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen10 :: HS Threads Dispatched */ #define cnl__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen10 :: L3 Total Throughput */ static uint64_t cnl__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Accesses 64 UMUL */ uint64_t tmp0 = cnl__compute_l3_cache__l3_accesses__read(perf, query, accumulator) * 64; return tmp0; } /* Compute Metrics L3 Cache Gen10 :: GTI Write Throughput */ #define cnl__compute_l3_cache__gti_write_throughput__read \ cnl__render_basic__gti_write_throughput__read /* Compute Metrics L3 Cache Gen10 :: L3 Shader Throughput */ #define cnl__compute_l3_cache__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen10 :: Samples Killed in FS */ #define cnl__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen10 :: SLM Bytes Written */ #define cnl__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen10 :: EU FPU1 Binary Instruction */ #define cnl__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen10 :: EU FPU1 Ternary Instruction */ #define cnl__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen10 :: EU Send Pipe Active */ #define cnl__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define cnl__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define cnl__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define cnl__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: SQ is full */ #define cnl__hdc_and_sf__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define cnl__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define cnl__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define cnl__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define cnl__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define cnl__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define cnl__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define cnl__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define cnl__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define cnl__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define cnl__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define cnl__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define cnl__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define cnl__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define cnl__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define cnl__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: Slice0 Subslice1 Non-sampler Shader Access Stalled On L3 */ static float cnl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: CS Threads Dispatched */ #define cnl__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: Slice0 Subslice2 Non-sampler Shader Access Stalled On L3 */ static float cnl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 6 READ B 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 6]; uint64_t tmp1 = accumulator[query->b_offset + 7]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: SLM Bytes Read */ #define cnl__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define cnl__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define cnl__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define cnl__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define cnl__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Slice1 Subslice0 Non-sampler Shader Access Stalled On L3 */ static float cnl__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ C 1 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: Rasterized Pixels */ #define cnl__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define cnl__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define cnl__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define cnl__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define cnl__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define cnl__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define cnl__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define cnl__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define cnl__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: Slice1 Subslice1 Non-sampler Shader Access Stalled On L3 */ static float cnl__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ C 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = accumulator[query->c_offset + 3]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: L3 Shader Throughput */ #define cnl__hdc_and_sf__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define cnl__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: Slice0 Subslice0 Non-sampler Shader Access Stalled On L3 */ static float cnl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ B 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = accumulator[query->b_offset + 3]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: SLM Bytes Written */ #define cnl__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define cnl__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define cnl__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define cnl__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define cnl__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define cnl__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: SQ is full */ #define cnl__l3_1__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: VS Send Pipe Active */ #define cnl__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define cnl__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define cnl__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define cnl__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define cnl__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define cnl__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ #define cnl__l3_1__l30_bank1_stalled__read \ bdw__render_basic__sampler1_busy__read /* Metric set L3_1 :: FS Threads Dispatched */ #define cnl__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define cnl__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define cnl__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define cnl__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: GPU Time Elapsed */ #define cnl__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define cnl__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define cnl__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define cnl__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define cnl__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define cnl__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define cnl__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define cnl__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define cnl__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define cnl__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank2 Active */ #define cnl__l3_1__l30_bank2_active__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define cnl__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__so_stall__read /* Metric set L3_1 :: Rasterized Pixels */ #define cnl__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: Slice1 L3 Bank2 Stalled */ #define cnl__l3_1__l31_bank2_stalled__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define cnl__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ #define cnl__l3_1__l30_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_1 :: DS Threads Dispatched */ #define cnl__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define cnl__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define cnl__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define cnl__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define cnl__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Shader Memory Accesses */ #define cnl__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define cnl__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: L3 Shader Throughput */ #define cnl__l3_1__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define cnl__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: SLM Bytes Written */ #define cnl__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define cnl__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_2 :: GPU Core Clocks */ #define cnl__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_2 :: EU Active */ #define cnl__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_2 :: Slice1 L3 Bank1 Stalled */ #define cnl__l3_2__l31_bank1_stalled__read \ bdw__render_basic__sampler1_busy__read /* Metric set L3_2 :: EU Both FPU Pipes Active */ #define cnl__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_2 :: SQ is full */ #define cnl__l3_2__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_2 :: VS Send Pipe Active */ #define cnl__l3_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_2 :: VS FPU1 Pipe Active */ #define cnl__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_2 :: GS Threads Dispatched */ #define cnl__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_2 :: Early Hi-Depth Test Fails */ #define cnl__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_2 :: FS Both FPU Active */ #define cnl__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_2 :: VS Threads Dispatched */ #define cnl__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_2 :: FS Threads Dispatched */ #define cnl__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_2 :: Shader Barrier Messages */ #define cnl__l3_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Slice1 L3 Bank0 Stalled */ #define cnl__l3_2__l31_bank0_stalled__read \ bdw__render_basic__sampler0_busy__read /* Metric set L3_2 :: Sampler Texels */ #define cnl__l3_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_2 :: Pixels Failing Tests */ #define cnl__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_2 :: GPU Time Elapsed */ #define cnl__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define cnl__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_2 :: AVG GPU Core Frequency */ #define cnl__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_2 :: Sampler Texels Misses */ #define cnl__l3_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_2 :: CS Threads Dispatched */ #define cnl__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_2 :: SLM Bytes Read */ #define cnl__l3_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_2 :: PS FPU1 Pipe Active */ #define cnl__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ #define cnl__l3_2__l30_bank2_stalled__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set L3_2 :: PS Send Pipeline Active */ #define cnl__l3_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_2 :: VS FPU0 Pipe Active */ #define cnl__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_2 :: GPU Busy */ #define cnl__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_2 :: Slice1 L3 Bank2 Active */ #define cnl__l3_2__l31_bank2_active__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set L3_2 :: Rasterized Pixels */ #define cnl__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_2 :: Slice1 L3 Bank1 Active */ #define cnl__l3_2__l31_bank1_active__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set L3_2 :: PS FPU0 Pipe Active */ #define cnl__l3_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_2 :: DS Threads Dispatched */ #define cnl__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_2 :: Samples Written */ #define cnl__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_2 :: EU Stall */ #define cnl__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_2 :: Slice1 L3 Bank0 Active */ #define cnl__l3_2__l31_bank0_active__read \ bdw__render_pipe_profile__so_stall__read /* Metric set L3_2 :: Samples Blended */ #define cnl__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_2 :: Early Depth Test Fails */ #define cnl__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_2 :: Shader Memory Accesses */ #define cnl__l3_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_2 :: HS Threads Dispatched */ #define cnl__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_2 :: L3 Shader Throughput */ #define cnl__l3_2__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set L3_2 :: Samples Killed in FS */ #define cnl__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_2 :: SLM Bytes Written */ #define cnl__l3_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_2 :: Shader Atomic Memory Accesses */ #define cnl__l3_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define cnl__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define cnl__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define cnl__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */ #define cnl__rasterizer_and_pixel_backend__rasterizer1_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define cnl__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define cnl__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define cnl__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define cnl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define cnl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define cnl__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define cnl__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ #define cnl__rasterizer_and_pixel_backend__pixel_values0_ready__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define cnl__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define cnl__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define cnl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define cnl__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define cnl__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define cnl__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define cnl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ #define cnl__rasterizer_and_pixel_backend__pixel_data0_ready__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define cnl__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define cnl__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define cnl__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define cnl__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define cnl__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */ #define cnl__rasterizer_and_pixel_backend__pixel_values1_ready__read \ bdw__render_pipe_profile__hs_stall__read /* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */ #define cnl__rasterizer_and_pixel_backend__ps_output1_available__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define cnl__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define cnl__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define cnl__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define cnl__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define cnl__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define cnl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define cnl__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define cnl__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */ #define cnl__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */ #define cnl__rasterizer_and_pixel_backend__pixel_data1_ready__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define cnl__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: SQ is full */ #define cnl__rasterizer_and_pixel_backend__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define cnl__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define cnl__rasterizer_and_pixel_backend__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define cnl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define cnl__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ #define cnl__rasterizer_and_pixel_backend__ps_output0_available__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define cnl__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler :: GPU Core Clocks */ #define cnl__sampler__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler :: EU Active */ #define cnl__sampler__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler :: Slice0 Subslice2 Input Available */ #define cnl__sampler__sampler02_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler :: EU Both FPU Pipes Active */ #define cnl__sampler__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler :: SQ is full */ #define cnl__sampler__gt_request_queue_full__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set Sampler :: VS Send Pipe Active */ #define cnl__sampler__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler :: Slice0 Subslice0 Input Available */ #define cnl__sampler__sampler00_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler :: VS FPU1 Pipe Active */ #define cnl__sampler__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler :: GS Threads Dispatched */ #define cnl__sampler__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler :: Slice1 Subslice0 Input Available */ #define cnl__sampler__sampler10_input_available__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set Sampler :: Early Hi-Depth Test Fails */ #define cnl__sampler__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler :: FS Both FPU Active */ #define cnl__sampler__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler :: VS Threads Dispatched */ #define cnl__sampler__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ #define cnl__sampler__sampler02_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler :: FS Threads Dispatched */ #define cnl__sampler__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler :: Shader Barrier Messages */ #define cnl__sampler__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice1 Input Available */ #define cnl__sampler__sampler01_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler :: Sampler Texels */ #define cnl__sampler__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler :: Pixels Failing Tests */ #define cnl__sampler__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler :: GPU Time Elapsed */ #define cnl__sampler__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define cnl__sampler__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler :: AVG GPU Core Frequency */ #define cnl__sampler__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler :: Sampler Texels Misses */ #define cnl__sampler__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler :: CS Threads Dispatched */ #define cnl__sampler__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler :: SLM Bytes Read */ #define cnl__sampler__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler :: PS FPU1 Pipe Active */ #define cnl__sampler__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler :: PS Send Pipeline Active */ #define cnl__sampler__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler :: VS FPU0 Pipe Active */ #define cnl__sampler__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler :: GPU Busy */ #define cnl__sampler__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler :: Slice1 Subslice1 Input Available */ #define cnl__sampler__sampler11_input_available__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set Sampler :: Rasterized Pixels */ #define cnl__sampler__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler :: PS FPU0 Pipe Active */ #define cnl__sampler__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler :: DS Threads Dispatched */ #define cnl__sampler__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler :: Samples Written */ #define cnl__sampler__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler :: EU Stall */ #define cnl__sampler__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler :: Samples Blended */ #define cnl__sampler__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler :: Early Depth Test Fails */ #define cnl__sampler__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ #define cnl__sampler__sampler00_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler :: Slice1 Subslice0 Sampler Output Ready */ #define cnl__sampler__sampler10_output_ready__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ #define cnl__sampler__sampler01_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler :: Shader Memory Accesses */ #define cnl__sampler__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler :: Slice1 Subslice1 Sampler Output Ready */ #define cnl__sampler__sampler11_output_ready__read \ bdw__render_pipe_profile__so_stall__read /* Metric set Sampler :: HS Threads Dispatched */ #define cnl__sampler__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler :: L3 Shader Throughput */ #define cnl__sampler__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set Sampler :: Samples Killed in FS */ #define cnl__sampler__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler :: SLM Bytes Written */ #define cnl__sampler__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler :: Shader Atomic Memory Accesses */ #define cnl__sampler__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define cnl__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define cnl__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define cnl__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: SQ is full */ #define cnl__tdl_1__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define cnl__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define cnl__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define cnl__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define cnl__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define cnl__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define cnl__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */ #define cnl__tdl_1__ps_thread11_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define cnl__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ static float cnl__tdl_1__non_ps_thread02_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 1 C 4 READ $GpuCoreClocks FDIV FSUB */ uint64_t tmp0 = accumulator[query->c_offset + 4]; double tmp1 = tmp0; double tmp2 = cnl__tdl_1__gpu_core_clocks__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; double tmp4 = 1 - tmp3; return tmp4; } /* Metric set TDL_1 :: Shader Barrier Messages */ #define cnl__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: Sampler Texels */ #define cnl__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define cnl__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */ static float cnl__tdl_1__non_ps_thread10_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 1 C 5 READ $GpuCoreClocks FDIV FSUB */ uint64_t tmp0 = accumulator[query->c_offset + 5]; double tmp1 = tmp0; double tmp2 = cnl__tdl_1__gpu_core_clocks__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; double tmp4 = 1 - tmp3; return tmp4; } /* Metric set TDL_1 :: GPU Time Elapsed */ #define cnl__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define cnl__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define cnl__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define cnl__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ static float cnl__tdl_1__non_ps_thread00_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 1 C 2 READ $GpuCoreClocks FDIV FSUB */ uint64_t tmp0 = accumulator[query->c_offset + 2]; double tmp1 = tmp0; double tmp2 = cnl__tdl_1__gpu_core_clocks__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; double tmp4 = 1 - tmp3; return tmp4; } /* Metric set TDL_1 :: CS Threads Dispatched */ #define cnl__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define cnl__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define cnl__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: PS Send Pipeline Active */ #define cnl__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define cnl__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: GPU Busy */ #define cnl__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ #define cnl__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_1 :: Rasterized Pixels */ #define cnl__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define cnl__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define cnl__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: Samples Written */ #define cnl__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: EU Stall */ #define cnl__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: Samples Blended */ #define cnl__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define cnl__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ #define cnl__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */ #define cnl__tdl_1__ps_thread10_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */ static float cnl__tdl_1__non_ps_thread11_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 1 C 6 READ $GpuCoreClocks FDIV FSUB */ uint64_t tmp0 = accumulator[query->c_offset + 6]; double tmp1 = tmp0; double tmp2 = cnl__tdl_1__gpu_core_clocks__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; double tmp4 = 1 - tmp3; return tmp4; } /* Metric set TDL_1 :: Shader Memory Accesses */ #define cnl__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: HS Threads Dispatched */ #define cnl__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ #define cnl__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define cnl__tdl_1__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define cnl__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: SLM Bytes Written */ #define cnl__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define cnl__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ static float cnl__tdl_1__non_ps_thread01_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 1 C 3 READ $GpuCoreClocks FDIV FSUB */ uint64_t tmp0 = accumulator[query->c_offset + 3]; double tmp1 = tmp0; double tmp2 = cnl__tdl_1__gpu_core_clocks__read(perf, query, accumulator); double tmp3 = tmp2 ? tmp1 / tmp2 : 0; double tmp4 = 1 - tmp3; return tmp4; } /* Metric set TDL_2 :: GPU Core Clocks */ #define cnl__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define cnl__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define cnl__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */ #define cnl__tdl_2__thread_header11_ready_port1__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define cnl__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define cnl__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define cnl__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define cnl__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define cnl__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define cnl__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define cnl__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Shader Barrier Messages */ #define cnl__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Sampler Texels */ #define cnl__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define cnl__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ #define cnl__tdl_2__thread_header01_ready_port0__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ #define cnl__tdl_2__thread_header01_ready_port1__read \ bdw__render_pipe_profile__hs_stall__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define cnl__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define cnl__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define cnl__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define cnl__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: CS Threads Dispatched */ #define cnl__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SQ is full */ #define cnl__tdl_2__gt_request_queue_full__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_2 :: SLM Bytes Read */ #define cnl__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */ #define cnl__tdl_2__thread_header11_ready_port0__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define cnl__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define cnl__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define cnl__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define cnl__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ #define cnl__tdl_2__thread_header02_ready_port1__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ #define cnl__tdl_2__thread_header02_ready_port0__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_2 :: Rasterized Pixels */ #define cnl__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define cnl__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define cnl__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define cnl__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */ #define cnl__tdl_2__thread_header10_ready_port1__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_2 :: EU Stall */ #define cnl__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define cnl__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define cnl__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Shader Memory Accesses */ #define cnl__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define cnl__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: L3 Shader Throughput */ #define cnl__tdl_2__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define cnl__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: SLM Bytes Written */ #define cnl__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */ #define cnl__tdl_2__thread_header10_ready_port0__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ #define cnl__tdl_2__thread_header00_ready_port0__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define cnl__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ #define cnl__tdl_2__thread_header00_ready_port1__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set TestOa :: TestCounter7 */ #define cnl__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* Metric set TestOa :: GPU Time Elapsed */ #define cnl__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TestOa :: GPU Core Clocks */ #define cnl__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TestOa :: AVG GPU Core Frequency */ #define cnl__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TestOa :: AVG GPU Core Frequency */ #define cnl__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TestOa :: TestCounter8 */ #define cnl__test_oa__counter8__read \ hsw__memory_reads__gpu_core_clocks__read /* Metric set TestOa :: TestCounter4 */ #define cnl__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Metric set TestOa :: TestCounter5 */ #define cnl__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* Metric set TestOa :: TestCounter6 */ #define cnl__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* Metric set TestOa :: TestCounter3 */ #define cnl__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* Metric set TestOa :: TestCounter0 */ #define cnl__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Metric set TestOa :: TestCounter1 */ #define cnl__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* Metric set TestOa :: TestCounter2 */ #define cnl__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read /* Render Metrics Basic Gen11 :: GPU Core Clocks */ #define icl__render_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics Basic Gen11 :: EU Active */ #define icl__render_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics Basic Gen11 :: EU Both FPU Pipes Active */ #define icl__render_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Render Metrics Basic Gen11 :: Sampler Cache Misses */ static uint64_t icl__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ C 5 READ UADD 8 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = accumulator[query->c_offset + 5]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 8; return tmp3; } /* Render Metrics Basic Gen11 :: VS Send Pipe Active */ #define icl__render_basic__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics Basic Gen11 :: VS FPU1 Pipe Active */ #define icl__render_basic__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Render Metrics Basic Gen11 :: GS Threads Dispatched */ #define icl__render_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics Basic Gen11 :: Early Hi-Depth Test Fails */ #define icl__render_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics Basic Gen11 :: VS Threads Dispatched */ #define icl__render_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics Basic Gen11 :: FS Threads Dispatched */ #define icl__render_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics Basic Gen11 :: Sampler00 Busy */ #define icl__render_basic__sampler00_busy__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics Basic Gen11 :: Samplers Busy */ #define icl__render_basic__samplers_busy__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics Basic Gen11 :: Shader Barrier Messages */ #define icl__render_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen11 :: Sampler Texels */ #define icl__render_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics Basic Gen11 :: Pixels Failing Tests */ #define icl__render_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics Basic Gen11 :: GPU Time Elapsed */ #define icl__render_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics Basic Gen11 :: AVG GPU Core Frequency */ #define icl__render_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics Basic Gen11 :: AVG GPU Core Frequency */ #define icl__render_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics Basic Gen11 :: Sampler Texels Misses */ #define icl__render_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics Basic Gen11 :: CS Threads Dispatched */ #define icl__render_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics Basic Gen11 :: Sampler00 Bottleneck */ #define icl__render_basic__sampler00_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics Basic Gen11 :: SLM Bytes Read */ #define icl__render_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics Basic Gen11 :: GTI Read Throughput */ static uint64_t icl__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 B 1 READ B 3 READ UADD B 4 READ UADD B 5 READ UADD UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = accumulator[query->b_offset + 3]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->b_offset + 4]; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = accumulator[query->b_offset + 5]; uint64_t tmp6 = tmp4 + tmp5; uint64_t tmp7 = 64 * tmp6; return tmp7; } /* Render Metrics Basic Gen11 :: PS FPU1 Pipe Active */ #define icl__render_basic__ps_fpu1_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Render Metrics Basic Gen11 :: PS Send Pipeline Active */ #define icl__render_basic__ps_send_active__read \ bdw__render_basic__ps_fpu0_active__read /* Render Metrics Basic Gen11 :: Rasterized Pixels */ #define icl__render_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics Basic Gen11 :: GPU Busy */ #define icl__render_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics Basic Gen11 :: VS FPU0 Pipe Active */ #define icl__render_basic__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Render Metrics Basic Gen11 :: PS FPU0 Pipe Active */ #define icl__render_basic__ps_fpu0_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Render Metrics Basic Gen11 :: DS Threads Dispatched */ #define icl__render_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics Basic Gen11 :: Samples Written */ #define icl__render_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics Basic Gen11 :: EU Stall */ #define icl__render_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics Basic Gen11 :: Samples Blended */ #define icl__render_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics Basic Gen11 :: Early Depth Test Fails */ #define icl__render_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics Basic Gen11 :: Samplers Bottleneck */ #define icl__render_basic__sampler_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics Basic Gen11 :: Shader Memory Accesses */ #define icl__render_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics Basic Gen11 :: HS Threads Dispatched */ #define icl__render_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics Basic Gen11 :: GTI Write Throughput */ static uint64_t icl__render_basic__gti_write_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 B 0 READ B 2 READ UADD UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 2]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = 64 * tmp2; return tmp3; } /* Render Metrics Basic Gen11 :: L3 Shader Throughput */ #define icl__render_basic__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Render Metrics Basic Gen11 :: Samples Killed in FS */ #define icl__render_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics Basic Gen11 :: SLM Bytes Written */ #define icl__render_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics Basic Gen11 :: Shader Atomic Memory Accesses */ #define icl__render_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen11 :: GPU Core Clocks */ #define icl__compute_basic__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics Basic Gen11 :: EU Active */ #define icl__compute_basic__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics Basic Gen11 :: Untyped Bytes Read */ static uint64_t icl__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 3 READ C 2 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 3]; uint64_t tmp1 = accumulator[query->c_offset + 2]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices; uint64_t tmp4 = tmp3 * 32; return tmp4; } /* Compute Metrics Basic Gen11 :: EU Both FPU Pipes Active */ #define icl__compute_basic__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics Basic Gen11 :: Typed Bytes Written */ static uint64_t icl__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ C 4 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = accumulator[query->c_offset + 4]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices; uint64_t tmp4 = tmp3 * 32; return tmp4; } /* Compute Metrics Basic Gen11 :: EU AVG IPC Rate */ #define icl__compute_basic__eu_avg_ipc_rate__read \ cnl__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics Basic Gen11 :: GS Threads Dispatched */ #define icl__compute_basic__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics Basic Gen11 :: Early Hi-Depth Test Fails */ #define icl__compute_basic__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics Basic Gen11 :: VS Threads Dispatched */ #define icl__compute_basic__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics Basic Gen11 :: FS Threads Dispatched */ #define icl__compute_basic__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics Basic Gen11 :: EU FPU1 Pipe Active */ #define icl__compute_basic__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics Basic Gen11 :: EU FPU0 Pipe Active */ #define icl__compute_basic__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics Basic Gen11 :: Shader Barrier Messages */ #define icl__compute_basic__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen11 :: Sampler Texels */ #define icl__compute_basic__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics Basic Gen11 :: Pixels Failing Tests */ #define icl__compute_basic__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics Basic Gen11 :: Typed Atomics Accesses */ static uint64_t icl__compute_basic__typed_atomics__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 4 READ B 5 READ FADD 2 FDIV $EuSubslicesTotalCount FMUL */ uint64_t tmp0 = accumulator[query->b_offset + 4]; uint64_t tmp1 = accumulator[query->b_offset + 5]; double tmp2 = tmp0 + tmp1; double tmp3 = tmp2; double tmp4 = 2; double tmp5 = tmp4 ? tmp3 / tmp4 : 0; double tmp6 = tmp5 * perf->sys_vars.n_eu_sub_slices; return tmp6; } /* Compute Metrics Basic Gen11 :: GPU Time Elapsed */ #define icl__compute_basic__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics Basic Gen11 :: AVG GPU Core Frequency */ #define icl__compute_basic__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics Basic Gen11 :: AVG GPU Core Frequency */ #define icl__compute_basic__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics Basic Gen11 :: Sampler Texels Misses */ #define icl__compute_basic__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics Basic Gen11 :: CS Threads Dispatched */ #define icl__compute_basic__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics Basic Gen11 :: SLM Bytes Read */ #define icl__compute_basic__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics Basic Gen11 :: GTI Read Throughput */ static uint64_t icl__compute_basic__gti_read_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 B 1 READ B 3 READ UADD B 7 READ UADD B 6 READ UADD UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 1]; uint64_t tmp1 = accumulator[query->b_offset + 3]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->b_offset + 7]; uint64_t tmp4 = tmp2 + tmp3; uint64_t tmp5 = accumulator[query->b_offset + 6]; uint64_t tmp6 = tmp4 + tmp5; uint64_t tmp7 = 64 * tmp6; return tmp7; } /* Compute Metrics Basic Gen11 :: Untyped Writes */ static uint64_t icl__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 1 READ C 0 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 1]; uint64_t tmp1 = accumulator[query->c_offset + 0]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices; uint64_t tmp4 = tmp3 * 32; return tmp4; } /* Compute Metrics Basic Gen11 :: GPU Busy */ #define icl__compute_basic__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics Basic Gen11 :: Rasterized Pixels */ #define icl__compute_basic__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics Basic Gen11 :: Typed Bytes Read */ static uint64_t icl__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ C 6 READ UADD $EuSubslicesTotalCount UMUL 32 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = accumulator[query->c_offset + 6]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * perf->sys_vars.n_eu_sub_slices; uint64_t tmp4 = tmp3 * 32; return tmp4; } /* Compute Metrics Basic Gen11 :: DS Threads Dispatched */ #define icl__compute_basic__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics Basic Gen11 :: EU Thread Occupancy */ #define icl__compute_basic__eu_thread_occupancy__read \ cnl__compute_basic__eu_thread_occupancy__read /* Compute Metrics Basic Gen11 :: EU Stall */ #define icl__compute_basic__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics Basic Gen11 :: Samples Blended */ #define icl__compute_basic__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics Basic Gen11 :: Early Depth Test Fails */ #define icl__compute_basic__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics Basic Gen11 :: Shader Memory Accesses */ #define icl__compute_basic__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics Basic Gen11 :: HS Threads Dispatched */ #define icl__compute_basic__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics Basic Gen11 :: GTI Write Throughput */ #define icl__compute_basic__gti_write_throughput__read \ icl__render_basic__gti_write_throughput__read /* Compute Metrics Basic Gen11 :: L3 Shader Throughput */ #define icl__compute_basic__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Compute Metrics Basic Gen11 :: Samples Killed in FS */ #define icl__compute_basic__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics Basic Gen11 :: SLM Bytes Written */ #define icl__compute_basic__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics Basic Gen11 :: Samples Written */ #define icl__compute_basic__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics Basic Gen11 :: Shader Atomic Memory Accesses */ #define icl__compute_basic__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics Basic Gen11 :: EU Send Pipe Active */ #define icl__compute_basic__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* ComputeExtended Gen11 :: UntypedWritesPerCacheLine */ static float icl__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ B 1 READ FADD C 2 READ FADD C 3 READ FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = accumulator[query->b_offset + 1]; double tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->c_offset + 2]; double tmp4 = tmp2 + tmp3; uint64_t tmp5 = accumulator[query->c_offset + 3]; double tmp6 = tmp4; double tmp7 = tmp5; double tmp8 = tmp7 ? tmp6 / tmp7 : 0; return tmp8; } /* ComputeExtended Gen11 :: Eu Typed Atomics 00 */ #define icl__compute_extended__eu_typed_atomics00__read \ hsw__compute_extended__eu_typed_reads0__read /* ComputeExtended Gen11 :: Typed Atomics 00 */ #define icl__compute_extended__typed_atomics00__read \ hsw__memory_reads__gpu_core_clocks__read /* ComputeExtended Gen11 :: TypedAtomicsPerCacheLine */ static float icl__compute_extended__typed_atomics_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedAtomics00 $TypedAtomics00 FDIV */ double tmp0 = icl__compute_extended__eu_typed_atomics00__read(perf, query, accumulator); double tmp1 = icl__compute_extended__typed_atomics00__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* ComputeExtended Gen11 :: Eu 64 Untyped Reads 00 */ static float icl__compute_extended__eu_a64_untyped_reads00__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 5 READ C 1 READ FADD B 6 READ FADD */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = accumulator[query->c_offset + 1]; double tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->b_offset + 6]; double tmp4 = tmp2 + tmp3; return tmp4; } /* ComputeExtended Gen11 :: Eu A32 Untyped Writes 00 */ static uint64_t icl__compute_extended__eu_a32_untyped_writes00__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ B 1 READ UADD */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = accumulator[query->b_offset + 1]; uint64_t tmp2 = tmp0 + tmp1; return tmp2; } /* ComputeExtended Gen11 :: GPU Core Clocks */ #define icl__compute_extended__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* ComputeExtended Gen11 :: GPU Time Elapsed */ #define icl__compute_extended__gpu_time__read \ hsw__render_basic__gpu_time__read /* ComputeExtended Gen11 :: AVG GPU Core Frequency */ #define icl__compute_extended__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* ComputeExtended Gen11 :: AVG GPU Core Frequency */ #define icl__compute_extended__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* ComputeExtended Gen11 :: CS Threads Dispatched */ #define icl__compute_extended__cs_threads__read \ bdw__render_basic__cs_threads__read /* ComputeExtended Gen11 :: Eu Typed Reads 00 */ #define icl__compute_extended__eu_typed_reads00__read \ hsw__compute_extended__eu_typed_writes0__read /* ComputeExtended Gen11 :: Eu Typed Writes 00 */ #define icl__compute_extended__eu_typed_writes00__read \ hsw__compute_extended__eu_untyped_atomics0__read /* ComputeExtended Gen11 :: Typed Writes 00 */ #define icl__compute_extended__typed_writes00__read \ hsw__memory_reads__gti_memory_reads__read /* ComputeExtended Gen11 :: TypedWritesPerCacheLine */ static float icl__compute_extended__typed_writes_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedWrites00 $TypedWrites00 FDIV */ double tmp0 = icl__compute_extended__eu_typed_writes00__read(perf, query, accumulator); double tmp1 = icl__compute_extended__typed_writes00__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* ComputeExtended Gen11 :: GPU Busy */ #define icl__compute_extended__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* ComputeExtended Gen11 :: Untyped Writes 00 */ #define icl__compute_extended__untyped_writes00__read \ hsw__compute_extended__untyped_reads0__read /* ComputeExtended Gen11 :: Untyped Reads 00 */ #define icl__compute_extended__untyped_reads00__read \ hsw__compute_extended__typed_atomics0__read /* ComputeExtended Gen11 :: Eu A64 Untyped Writes 00 */ #define icl__compute_extended__eu_a64_untyped_writes00__read \ hsw__render_basic__gpu_core_clocks__read /* ComputeExtended Gen11 :: UntypedReadsPerCacheLine */ static float icl__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 5 READ C 1 READ FADD B 6 READ FADD FADD C 4 READ FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 5]; uint64_t tmp2 = accumulator[query->c_offset + 1]; double tmp3 = tmp1 + tmp2; uint64_t tmp4 = accumulator[query->b_offset + 6]; double tmp5 = tmp3 + tmp4; double tmp6 = tmp0 + tmp5; uint64_t tmp7 = accumulator[query->c_offset + 4]; double tmp8 = tmp6; double tmp9 = tmp7; double tmp10 = tmp9 ? tmp8 / tmp9 : 0; return tmp10; } /* ComputeExtended Gen11 :: Typed Reads 00 */ #define icl__compute_extended__typed_reads00__read \ hsw__memory_reads__llc_read_accesses__read /* ComputeExtended Gen11 :: TypedReadsPerCacheLine */ static float icl__compute_extended__typed_reads_per_cache_line__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $EuTypedReads00 $TypedReads00 FDIV */ double tmp0 = icl__compute_extended__eu_typed_reads00__read(perf, query, accumulator); double tmp1 = icl__compute_extended__typed_reads00__read(perf, query, accumulator); double tmp2 = tmp1 ? tmp0 / tmp1 : 0; return tmp2; } /* ComputeExtended Gen11 :: Eu A32 Untyped Reads 00 */ #define icl__compute_extended__eu_a32_untyped_reads00__read \ hsw__compute_extended__eu_untyped_reads0__read /* Compute Metrics L3 Cache Gen11 :: GPU Core Clocks */ #define icl__compute_l3_cache__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Compute Metrics L3 Cache Gen11 :: EU Active */ #define icl__compute_l3_cache__eu_active__read \ bdw__render_basic__eu_active__read /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank3 Accesses */ static uint64_t icl__compute_l3_cache__l3_bank03_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank0 Accesses */ static uint64_t icl__compute_l3_cache__l3_bank00_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 7 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 7]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank1 Accesses */ #define icl__compute_l3_cache__l3_bank01_accesses__read \ hsw__memory_writes__llc_wr_accesses__read /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank2 Accesses */ static uint64_t icl__compute_l3_cache__l3_bank02_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 5 READ 2 UMUL */ uint64_t tmp0 = accumulator[query->c_offset + 5]; uint64_t tmp1 = tmp0 * 2; return tmp1; } /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank4 Accesses */ #define icl__compute_l3_cache__l3_bank04_accesses__read \ bdw__memory_reads__gti_ring_accesses__read /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank5 Accesses */ #define icl__compute_l3_cache__l3_bank05_accesses__read \ bdw__compute_l3_cache__l3_bank10_accesses__read /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank6 Accesses */ #define icl__compute_l3_cache__l3_bank06_accesses__read \ bdw__compute_l3_cache__l3_bank01_accesses__read /* Compute Metrics L3 Cache Gen11 :: Slice0 L3 Bank7 Accesses */ #define icl__compute_l3_cache__l3_bank07_accesses__read \ bdw__compute_l3_cache__l3_bank00_accesses__read /* Compute Metrics L3 Cache Gen11 :: L3 Accesses */ static uint64_t icl__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Bank00Accesses $L3Bank01Accesses UADD $L3Bank02Accesses UADD $L3Bank03Accesses UADD $L3Bank04Accesses UADD $L3Bank05Accesses UADD $L3Bank06Accesses UADD $L3Bank07Accesses UADD */ uint64_t tmp0 = icl__compute_l3_cache__l3_bank00_accesses__read(perf, query, accumulator) + icl__compute_l3_cache__l3_bank01_accesses__read(perf, query, accumulator); uint64_t tmp1 = tmp0 + icl__compute_l3_cache__l3_bank02_accesses__read(perf, query, accumulator); uint64_t tmp2 = tmp1 + icl__compute_l3_cache__l3_bank03_accesses__read(perf, query, accumulator); uint64_t tmp3 = tmp2 + icl__compute_l3_cache__l3_bank04_accesses__read(perf, query, accumulator); uint64_t tmp4 = tmp3 + icl__compute_l3_cache__l3_bank05_accesses__read(perf, query, accumulator); uint64_t tmp5 = tmp4 + icl__compute_l3_cache__l3_bank06_accesses__read(perf, query, accumulator); uint64_t tmp6 = tmp5 + icl__compute_l3_cache__l3_bank07_accesses__read(perf, query, accumulator); return tmp6; } /* Compute Metrics L3 Cache Gen11 :: EU Both FPU Pipes Active */ #define icl__compute_l3_cache__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Compute Metrics L3 Cache Gen11 :: L3 Sampler Throughput */ static uint64_t icl__compute_l3_cache__l3_sampler_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 64 B 7 READ B 6 READ UADD 8 UMUL UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = accumulator[query->b_offset + 6]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 8; uint64_t tmp4 = 64 * tmp3; return tmp4; } /* Compute Metrics L3 Cache Gen11 :: EU AVG IPC Rate */ #define icl__compute_l3_cache__eu_avg_ipc_rate__read \ cnl__compute_basic__eu_avg_ipc_rate__read /* Compute Metrics L3 Cache Gen11 :: EU FPU0 Binary Instruction */ #define icl__compute_l3_cache__eu_binary_fpu0_instruction__read \ bdw__render_basic__ps_send_active__read /* Compute Metrics L3 Cache Gen11 :: GS Threads Dispatched */ #define icl__compute_l3_cache__gs_threads__read \ hsw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen11 :: Early Hi-Depth Test Fails */ #define icl__compute_l3_cache__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Compute Metrics L3 Cache Gen11 :: VS Threads Dispatched */ #define icl__compute_l3_cache__vs_threads__read \ bdw__render_basic__vs_threads__read /* Compute Metrics L3 Cache Gen11 :: FS Threads Dispatched */ #define icl__compute_l3_cache__ps_threads__read \ bdw__render_basic__ps_threads__read /* Compute Metrics L3 Cache Gen11 :: EU FPU0 Hybrid Instruction */ #define icl__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Compute Metrics L3 Cache Gen11 :: EU FPU1 Pipe Active */ #define icl__compute_l3_cache__fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Compute Metrics L3 Cache Gen11 :: EU FPU0 Pipe Active */ #define icl__compute_l3_cache__fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Compute Metrics L3 Cache Gen11 :: Shader Barrier Messages */ #define icl__compute_l3_cache__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen11 :: L3 Misses */ static uint64_t icl__compute_l3_cache__l3_misses__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: 2 B 5 READ B 4 READ UADD UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 5]; uint64_t tmp1 = accumulator[query->b_offset + 4]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = 2 * tmp2; return tmp3; } /* Compute Metrics L3 Cache Gen11 :: EU FPU0 Move Instruction */ #define icl__compute_l3_cache__eu_move_fpu0_instruction__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Compute Metrics L3 Cache Gen11 :: Sampler Accesses */ #define icl__compute_l3_cache__sampler_accesses__read \ bdw__render_pipe_profile__sampler_accesses__read /* Compute Metrics L3 Cache Gen11 :: Sampler Texels */ #define icl__compute_l3_cache__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Compute Metrics L3 Cache Gen11 :: Pixels Failing Tests */ #define icl__compute_l3_cache__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Compute Metrics L3 Cache Gen11 :: EU FPU1 Hybrid Instruction */ #define icl__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Compute Metrics L3 Cache Gen11 :: GPU Time Elapsed */ #define icl__compute_l3_cache__gpu_time__read \ hsw__render_basic__gpu_time__read /* Compute Metrics L3 Cache Gen11 :: AVG GPU Core Frequency */ #define icl__compute_l3_cache__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Compute Metrics L3 Cache Gen11 :: AVG GPU Core Frequency */ #define icl__compute_l3_cache__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Compute Metrics L3 Cache Gen11 :: Sampler Texels Misses */ #define icl__compute_l3_cache__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Compute Metrics L3 Cache Gen11 :: CS Threads Dispatched */ #define icl__compute_l3_cache__cs_threads__read \ bdw__render_basic__cs_threads__read /* Compute Metrics L3 Cache Gen11 :: L3 Lookup Accesses w/o IC */ static uint64_t icl__compute_l3_cache__l3_lookups__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 7 READ B 6 READ UADD 8 UMUL A 32 READ UADD */ uint64_t tmp0 = accumulator[query->b_offset + 7]; uint64_t tmp1 = accumulator[query->b_offset + 6]; uint64_t tmp2 = tmp0 + tmp1; uint64_t tmp3 = tmp2 * 8; uint64_t tmp4 = accumulator[query->a_offset + 32]; uint64_t tmp5 = tmp3 + tmp4; return tmp5; } /* Compute Metrics L3 Cache Gen11 :: SLM Bytes Read */ #define icl__compute_l3_cache__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Compute Metrics L3 Cache Gen11 :: GTI Read Throughput */ static uint64_t icl__compute_l3_cache__gti_read_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Compute Metrics L3 Cache Gen11 :: GPU Busy */ #define icl__compute_l3_cache__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Compute Metrics L3 Cache Gen11 :: EU FPU0 Ternary Instruction */ #define icl__compute_l3_cache__eu_ternary_fpu0_instruction__read \ bdw__render_basic__ps_fpu0_active__read /* Compute Metrics L3 Cache Gen11 :: Shader Atomic Memory Accesses */ #define icl__compute_l3_cache__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Compute Metrics L3 Cache Gen11 :: Rasterized Pixels */ #define icl__compute_l3_cache__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Compute Metrics L3 Cache Gen11 :: GTI L3 Throughput */ static uint64_t icl__compute_l3_cache__gti_l3_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Misses 64 UMUL */ uint64_t tmp0 = icl__compute_l3_cache__l3_misses__read(perf, query, accumulator) * 64; return tmp0; } /* Compute Metrics L3 Cache Gen11 :: DS Threads Dispatched */ #define icl__compute_l3_cache__ds_threads__read \ bdw__render_basic__ds_threads__read /* Compute Metrics L3 Cache Gen11 :: Samples Written */ #define icl__compute_l3_cache__samples_written__read \ bdw__render_basic__samples_written__read /* Compute Metrics L3 Cache Gen11 :: EU FPU1 Move Instruction */ #define icl__compute_l3_cache__eu_move_fpu1_instruction__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Compute Metrics L3 Cache Gen11 :: EU Stall */ #define icl__compute_l3_cache__eu_stall__read \ bdw__render_basic__eu_stall__read /* Compute Metrics L3 Cache Gen11 :: Samples Blended */ #define icl__compute_l3_cache__samples_blended__read \ bdw__render_basic__samples_blended__read /* Compute Metrics L3 Cache Gen11 :: Early Depth Test Fails */ #define icl__compute_l3_cache__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Compute Metrics L3 Cache Gen11 :: Shader Memory Accesses */ #define icl__compute_l3_cache__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Compute Metrics L3 Cache Gen11 :: HS Threads Dispatched */ #define icl__compute_l3_cache__hs_threads__read \ bdw__render_basic__hs_threads__read /* Compute Metrics L3 Cache Gen11 :: L3 Total Throughput */ static uint64_t icl__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: $L3Accesses 64 UMUL */ uint64_t tmp0 = icl__compute_l3_cache__l3_accesses__read(perf, query, accumulator) * 64; return tmp0; } /* Compute Metrics L3 Cache Gen11 :: GTI Write Throughput */ static uint64_t icl__compute_l3_cache__gti_write_throughput__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 3 READ 64 UMUL */ uint64_t tmp0 = accumulator[query->b_offset + 3]; uint64_t tmp1 = tmp0 * 64; return tmp1; } /* Compute Metrics L3 Cache Gen11 :: L3 Shader Throughput */ #define icl__compute_l3_cache__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Compute Metrics L3 Cache Gen11 :: Samples Killed in FS */ #define icl__compute_l3_cache__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Compute Metrics L3 Cache Gen11 :: SLM Bytes Written */ #define icl__compute_l3_cache__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Compute Metrics L3 Cache Gen11 :: EU FPU1 Binary Instruction */ #define icl__compute_l3_cache__eu_binary_fpu1_instruction__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Compute Metrics L3 Cache Gen11 :: EU FPU1 Ternary Instruction */ #define icl__compute_l3_cache__eu_ternary_fpu1_instruction__read \ bdw__render_basic__ps_fpu1_active__read /* Compute Metrics L3 Cache Gen11 :: EU Send Pipe Active */ #define icl__compute_l3_cache__eu_send_active__read \ bdw__render_basic__vs_send_active__read /* Render Metrics for 3D Pipeline Profile Gen11 :: GPU Core Clocks */ #define icl__render_pipe_profile__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Render Metrics for 3D Pipeline Profile Gen11 :: EU Active */ #define icl__render_pipe_profile__eu_active__read \ bdw__render_basic__eu_active__read /* Render Metrics for 3D Pipeline Profile Gen11 :: VS Bottleneck */ #define icl__render_pipe_profile__vs_bottleneck__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Hi-Depth Bottleneck */ #define icl__render_pipe_profile__hi_depth_bottleneck__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: GS Bottleneck */ #define icl__render_pipe_profile__gs_bottleneck__read \ bdw__render_pipe_profile__so_stall__read /* Render Metrics for 3D Pipeline Profile Gen11 :: GS Threads Dispatched */ #define icl__render_pipe_profile__gs_threads__read \ hsw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Early Hi-Depth Test Fails */ #define icl__render_pipe_profile__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen11 :: VS Threads Dispatched */ #define icl__render_pipe_profile__vs_threads__read \ bdw__render_basic__vs_threads__read /* Render Metrics for 3D Pipeline Profile Gen11 :: FS Threads Dispatched */ #define icl__render_pipe_profile__ps_threads__read \ bdw__render_basic__ps_threads__read /* Render Metrics for 3D Pipeline Profile Gen11 :: BC Bottleneck */ #define icl__render_pipe_profile__bc_bottleneck__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: HS Stall */ #define icl__render_pipe_profile__hs_stall__read \ bdw__render_pipe_profile__so_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Shader Barrier Messages */ #define icl__render_pipe_profile__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Sampler Texels */ #define icl__render_pipe_profile__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Pixels Failing Tests */ #define icl__render_pipe_profile__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Render Metrics for 3D Pipeline Profile Gen11 :: GPU Time Elapsed */ #define icl__render_pipe_profile__gpu_time__read \ hsw__render_basic__gpu_time__read /* Render Metrics for 3D Pipeline Profile Gen11 :: AVG GPU Core Frequency */ #define icl__render_pipe_profile__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Render Metrics for 3D Pipeline Profile Gen11 :: AVG GPU Core Frequency */ #define icl__render_pipe_profile__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Render Metrics for 3D Pipeline Profile Gen11 :: Sampler Texels Misses */ #define icl__render_pipe_profile__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Render Metrics for 3D Pipeline Profile Gen11 :: CS Threads Dispatched */ #define icl__render_pipe_profile__cs_threads__read \ bdw__render_basic__cs_threads__read /* Render Metrics for 3D Pipeline Profile Gen11 :: VF Bottleneck */ #define icl__render_pipe_profile__vf_bottleneck__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: SLM Bytes Read */ #define icl__render_pipe_profile__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Strip-Fans Bottleneck */ #define icl__render_pipe_profile__sf_bottleneck__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: SF Stall */ #define icl__render_pipe_profile__sf_stall__read \ bdw__render_basic__sampler0_busy__read /* Render Metrics for 3D Pipeline Profile Gen11 :: GPU Busy */ #define icl__render_pipe_profile__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Render Metrics for 3D Pipeline Profile Gen11 :: HS Bottleneck */ #define icl__render_pipe_profile__hs_bottleneck__read \ bdw__render_pipe_profile__sf_stall__read /* Render Metrics for 3D Pipeline Profile Gen11 :: CL Stall */ #define icl__render_pipe_profile__cl_stall__read \ bdw__render_basic__sampler1_busy__read /* Render Metrics for 3D Pipeline Profile Gen11 :: SO Bottleneck */ #define icl__render_pipe_profile__so_bottleneck__read \ bdw__render_pipe_profile__ds_stall__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Rasterized Pixels */ #define icl__render_pipe_profile__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Render Metrics for 3D Pipeline Profile Gen11 :: DS Threads Dispatched */ #define icl__render_pipe_profile__ds_threads__read \ bdw__render_basic__ds_threads__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Samples Written */ #define icl__render_pipe_profile__samples_written__read \ bdw__render_basic__samples_written__read /* Render Metrics for 3D Pipeline Profile Gen11 :: DS Bottleneck */ #define icl__render_pipe_profile__ds_bottleneck__read \ bdw__render_pipe_profile__cl_stall__read /* Render Metrics for 3D Pipeline Profile Gen11 :: EU Stall */ #define icl__render_pipe_profile__eu_stall__read \ bdw__render_basic__eu_stall__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Clipper Bottleneck */ #define icl__render_pipe_profile__cl_bottleneck__read \ bdw__render_pipe_profile__hs_stall__read /* Render Metrics for 3D Pipeline Profile Gen11 :: DS Stall */ #define icl__render_pipe_profile__ds_stall__read \ bdw__render_basic__sampler1_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Early Depth Bottleneck */ #define icl__render_pipe_profile__early_depth_bottleneck__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Samples Blended */ #define icl__render_pipe_profile__samples_blended__read \ bdw__render_basic__samples_blended__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Early Depth Test Fails */ #define icl__render_pipe_profile__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Shader Memory Accesses */ #define icl__render_pipe_profile__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Render Metrics for 3D Pipeline Profile Gen11 :: HS Threads Dispatched */ #define icl__render_pipe_profile__hs_threads__read \ bdw__render_basic__hs_threads__read /* Render Metrics for 3D Pipeline Profile Gen11 :: L3 Shader Throughput */ #define icl__render_pipe_profile__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Samples Killed in FS */ #define icl__render_pipe_profile__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Render Metrics for 3D Pipeline Profile Gen11 :: SLM Bytes Written */ #define icl__render_pipe_profile__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Render Metrics for 3D Pipeline Profile Gen11 :: SO Stall */ #define icl__render_pipe_profile__so_stall__read \ bdw__render_basic__sampler0_bottleneck__read /* Render Metrics for 3D Pipeline Profile Gen11 :: Shader Atomic Memory Accesses */ #define icl__render_pipe_profile__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set HDCAndSF :: GPU Core Clocks */ #define icl__hdc_and_sf__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set HDCAndSF :: EU Active */ #define icl__hdc_and_sf__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set HDCAndSF :: EU Both FPU Pipes Active */ #define icl__hdc_and_sf__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set HDCAndSF :: SQ is full */ #define icl__hdc_and_sf__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set HDCAndSF :: VS Send Pipe Active */ #define icl__hdc_and_sf__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set HDCAndSF :: VS FPU1 Pipe Active */ #define icl__hdc_and_sf__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set HDCAndSF :: GS Threads Dispatched */ #define icl__hdc_and_sf__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ #define icl__hdc_and_sf__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set HDCAndSF :: FS Both FPU Active */ #define icl__hdc_and_sf__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set HDCAndSF :: VS Threads Dispatched */ #define icl__hdc_and_sf__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set HDCAndSF :: Polygon Data Ready */ #define icl__hdc_and_sf__poly_data_ready__read \ bdw__render_basic__sampler0_busy__read /* Metric set HDCAndSF :: FS Threads Dispatched */ #define icl__hdc_and_sf__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set HDCAndSF :: Shader Barrier Messages */ #define icl__hdc_and_sf__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Sampler Texels */ #define icl__hdc_and_sf__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set HDCAndSF :: Pixels Failing Tests */ #define icl__hdc_and_sf__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set HDCAndSF :: GPU Time Elapsed */ #define icl__hdc_and_sf__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define icl__hdc_and_sf__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set HDCAndSF :: AVG GPU Core Frequency */ #define icl__hdc_and_sf__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set HDCAndSF :: Sampler Texels Misses */ #define icl__hdc_and_sf__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set HDCAndSF :: Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3 */ static float icl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 2 READ C 1 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 2]; uint64_t tmp1 = accumulator[query->c_offset + 1]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: CS Threads Dispatched */ #define icl__hdc_and_sf__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set HDCAndSF :: Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3 */ static float icl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 4 READ C 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 4]; uint64_t tmp1 = accumulator[query->c_offset + 3]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: SLM Bytes Read */ #define icl__hdc_and_sf__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set HDCAndSF :: PS FPU1 Pipe Active */ #define icl__hdc_and_sf__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set HDCAndSF :: PS Send Pipeline Active */ #define icl__hdc_and_sf__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set HDCAndSF :: VS FPU0 Pipe Active */ #define icl__hdc_and_sf__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set HDCAndSF :: GPU Busy */ #define icl__hdc_and_sf__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set HDCAndSF :: Rasterized Pixels */ #define icl__hdc_and_sf__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set HDCAndSF :: PS FPU0 Pipe Active */ #define icl__hdc_and_sf__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set HDCAndSF :: DS Threads Dispatched */ #define icl__hdc_and_sf__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set HDCAndSF :: Samples Written */ #define icl__hdc_and_sf__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set HDCAndSF :: EU Stall */ #define icl__hdc_and_sf__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set HDCAndSF :: Samples Blended */ #define icl__hdc_and_sf__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set HDCAndSF :: Early Depth Test Fails */ #define icl__hdc_and_sf__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set HDCAndSF :: Shader Memory Accesses */ #define icl__hdc_and_sf__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set HDCAndSF :: HS Threads Dispatched */ #define icl__hdc_and_sf__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set HDCAndSF :: L3 Shader Throughput */ #define icl__hdc_and_sf__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set HDCAndSF :: Samples Killed in FS */ #define icl__hdc_and_sf__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set HDCAndSF :: Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3 */ static float icl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 0 READ B 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 7]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: SLM Bytes Written */ #define icl__hdc_and_sf__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set HDCAndSF :: Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3 */ static float icl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: C 6 READ C 5 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->c_offset + 6]; uint64_t tmp1 = accumulator[query->c_offset + 5]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__hdc_and_sf__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ #define icl__hdc_and_sf__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ #define icl__rasterizer_and_pixel_backend__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set RasterizerAndPixelBackend :: EU Active */ #define icl__rasterizer_and_pixel_backend__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ #define icl__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set RasterizerAndPixelBackend :: SQ is full */ #define icl__rasterizer_and_pixel_backend__gt_request_queue_full__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ #define icl__rasterizer_and_pixel_backend__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 PS Output Available */ #define icl__rasterizer_and_pixel_backend__ps_output00_available__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ #define icl__rasterizer_and_pixel_backend__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ #define icl__rasterizer_and_pixel_backend__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 PS Output Available */ #define icl__rasterizer_and_pixel_backend__ps_output01_available__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ #define icl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ #define icl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ #define icl__rasterizer_and_pixel_backend__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ #define icl__rasterizer_and_pixel_backend__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Pixel Values Ready */ #define icl__rasterizer_and_pixel_backend__pixel_values01_ready__read \ bdw__render_pipe_profile__so_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Post-EarlyZ Pixel Data Ready */ #define icl__rasterizer_and_pixel_backend__pixel_data00_ready__read \ bdw__render_basic__sampler1_busy__read /* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ #define icl__rasterizer_and_pixel_backend__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Sampler Texels */ #define icl__rasterizer_and_pixel_backend__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ #define icl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ #define icl__rasterizer_and_pixel_backend__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ #define icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ #define icl__rasterizer_and_pixel_backend__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pipe1 Post-EarlyZ Pixel Data Ready */ #define icl__rasterizer_and_pixel_backend__pixel_data01_ready__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ #define icl__rasterizer_and_pixel_backend__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ #define icl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ #define icl__rasterizer_and_pixel_backend__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ #define icl__rasterizer_and_pixel_backend__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ #define icl__rasterizer_and_pixel_backend__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ #define icl__rasterizer_and_pixel_backend__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: GPU Busy */ #define icl__rasterizer_and_pixel_backend__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ #define icl__rasterizer_and_pixel_backend__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set RasterizerAndPixelBackend :: Slice0 Pipe0 Pixel Values Ready */ #define icl__rasterizer_and_pixel_backend__pixel_values00_ready__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ #define icl__rasterizer_and_pixel_backend__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ #define icl__rasterizer_and_pixel_backend__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set RasterizerAndPixelBackend :: Samples Written */ #define icl__rasterizer_and_pixel_backend__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set RasterizerAndPixelBackend :: EU Stall */ #define icl__rasterizer_and_pixel_backend__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ #define icl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set RasterizerAndPixelBackend :: Samples Blended */ #define icl__rasterizer_and_pixel_backend__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ #define icl__rasterizer_and_pixel_backend__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ #define icl__rasterizer_and_pixel_backend__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ #define icl__rasterizer_and_pixel_backend__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ #define icl__rasterizer_and_pixel_backend__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ #define icl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ #define icl__rasterizer_and_pixel_backend__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ #define icl__rasterizer_and_pixel_backend__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set L3_1 :: GPU Core Clocks */ #define icl__l3_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set L3_1 :: EU Active */ #define icl__l3_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set L3_1 :: Slice0 L3 Bank1 Active */ #define icl__l3_1__l30_bank1_active__read \ bdw__render_pipe_profile__hs_stall__read /* Metric set L3_1 :: EU Both FPU Pipes Active */ #define icl__l3_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set L3_1 :: SQ is full */ #define icl__l3_1__gt_request_queue_full__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set L3_1 :: VS Send Pipe Active */ #define icl__l3_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set L3_1 :: VS FPU1 Pipe Active */ #define icl__l3_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set L3_1 :: GS Threads Dispatched */ #define icl__l3_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set L3_1 :: Early Hi-Depth Test Fails */ #define icl__l3_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set L3_1 :: FS Both FPU Active */ #define icl__l3_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set L3_1 :: VS Threads Dispatched */ #define icl__l3_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set L3_1 :: FS Threads Dispatched */ #define icl__l3_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set L3_1 :: Shader Barrier Messages */ #define icl__l3_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Sampler Texels */ #define icl__l3_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set L3_1 :: Pixels Failing Tests */ #define icl__l3_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set L3_1 :: Slice0 L3 Bank5 Active */ #define icl__l3_1__l30_bank5_active__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set L3_1 :: GPU Time Elapsed */ #define icl__l3_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define icl__l3_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set L3_1 :: AVG GPU Core Frequency */ #define icl__l3_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set L3_1 :: Sampler Texels Misses */ #define icl__l3_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set L3_1 :: CS Threads Dispatched */ #define icl__l3_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set L3_1 :: SLM Bytes Read */ #define icl__l3_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set L3_1 :: PS FPU1 Pipe Active */ #define icl__l3_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set L3_1 :: Slice0 L3 Bank3 Active */ #define icl__l3_1__l30_bank3_active__read \ bdw__render_pipe_profile__so_stall__read /* Metric set L3_1 :: PS Send Pipeline Active */ #define icl__l3_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set L3_1 :: VS FPU0 Pipe Active */ #define icl__l3_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set L3_1 :: GPU Busy */ #define icl__l3_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set L3_1 :: Slice0 L3 Bank6 Active */ #define icl__l3_1__l30_bank6_active__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set L3_1 :: Slice0 L3 Bank2 Active */ #define icl__l3_1__l30_bank2_active__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set L3_1 :: Slice0 L3 Bank0 Active */ #define icl__l3_1__l30_bank0_active__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Metric set L3_1 :: Rasterized Pixels */ #define icl__l3_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set L3_1 :: PS FPU0 Pipe Active */ #define icl__l3_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set L3_1 :: DS Threads Dispatched */ #define icl__l3_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set L3_1 :: Samples Written */ #define icl__l3_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set L3_1 :: EU Stall */ #define icl__l3_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set L3_1 :: Samples Blended */ #define icl__l3_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set L3_1 :: Early Depth Test Fails */ #define icl__l3_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set L3_1 :: Slice0 L3 Bank7 Active */ #define icl__l3_1__l30_bank7_active__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set L3_1 :: Slice0 L3 Bank4 Active */ #define icl__l3_1__l30_bank4_active__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set L3_1 :: Shader Memory Accesses */ #define icl__l3_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set L3_1 :: HS Threads Dispatched */ #define icl__l3_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set L3_1 :: L3 Shader Throughput */ #define icl__l3_1__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set L3_1 :: Samples Killed in FS */ #define icl__l3_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set L3_1 :: SLM Bytes Written */ #define icl__l3_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set L3_1 :: Shader Atomic Memory Accesses */ #define icl__l3_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Gen11 L2Bank0 stalled metric set :: GPU Core Clocks */ #define icl__l3_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gen11 L2Bank0 stalled metric set :: EU Active */ #define icl__l3_2__eu_active__read \ bdw__render_basic__eu_active__read /* Gen11 L2Bank0 stalled metric set :: EU Both FPU Pipes Active */ #define icl__l3_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Gen11 L2Bank0 stalled metric set :: VS Send Pipe Active */ #define icl__l3_2__vs_send_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Gen11 L2Bank0 stalled metric set :: VS FPU1 Pipe Active */ #define icl__l3_2__vs_fpu1_active__read \ bdw__render_basic__vs_send_active__read /* Gen11 L2Bank0 stalled metric set :: GS Threads Dispatched */ #define icl__l3_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Gen11 L2Bank0 stalled metric set :: Early Hi-Depth Test Fails */ #define icl__l3_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Gen11 L2Bank0 stalled metric set :: FS Both FPU Active */ #define icl__l3_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_send_active__read /* Gen11 L2Bank0 stalled metric set :: VS Threads Dispatched */ #define icl__l3_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Gen11 L2Bank0 stalled metric set :: FS Threads Dispatched */ #define icl__l3_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Gen11 L2Bank0 stalled metric set :: Pixels Failing Tests */ #define icl__l3_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Gen11 L2Bank0 stalled metric set :: GPU Time Elapsed */ #define icl__l3_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gen11 L2Bank0 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gen11 L2Bank0 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gen11 L2Bank0 stalled metric set :: CS Threads Dispatched */ #define icl__l3_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Gen11 L2Bank0 stalled metric set :: PS FPU1 Pipe Active */ #define icl__l3_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu0_active__read /* Gen11 L2Bank0 stalled metric set :: PS Send Pipeline Active */ #define icl__l3_2__ps_send_active__read \ bdw__render_basic__ps_fpu1_active__read /* Gen11 L2Bank0 stalled metric set :: Rasterized Pixels */ #define icl__l3_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Gen11 L2Bank0 stalled metric set :: GPU Busy */ #define icl__l3_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gen11 L2Bank0 stalled metric set :: VS FPU0 Pipe Active */ #define icl__l3_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu1_active__read /* Gen11 L2Bank0 stalled metric set :: PS FPU0 Pipe Active */ #define icl__l3_2__ps_fpu0_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Gen11 L2Bank0 stalled metric set :: Slice0 L3 Bank0 Stalled */ static float icl__l3_2__l30_bank0_stalled__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 0 READ B 1 READ FADD B 2 READ FADD B 3 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 1]; double tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->b_offset + 2]; double tmp4 = tmp2 + tmp3; uint64_t tmp5 = accumulator[query->b_offset + 3]; double tmp6 = tmp4 + tmp5; double tmp7 = tmp6; double tmp8 = 4; double tmp9 = tmp8 ? tmp7 / tmp8 : 0; uint64_t tmp10 = tmp9 * 100; double tmp11 = tmp10; double tmp12 = icl__l3_2__gpu_core_clocks__read(perf, query, accumulator); double tmp13 = tmp12 ? tmp11 / tmp12 : 0; return tmp13; } /* Gen11 L2Bank0 stalled metric set :: DS Threads Dispatched */ #define icl__l3_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Gen11 L2Bank0 stalled metric set :: Samples Written */ #define icl__l3_2__samples_written__read \ bdw__render_basic__samples_written__read /* Gen11 L2Bank0 stalled metric set :: EU Stall */ #define icl__l3_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Gen11 L2Bank0 stalled metric set :: Samples Blended */ #define icl__l3_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Gen11 L2Bank0 stalled metric set :: Early Depth Test Fails */ #define icl__l3_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Gen11 L2Bank0 stalled metric set :: HS Threads Dispatched */ #define icl__l3_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Gen11 L2Bank0 stalled metric set :: Samples Killed in FS */ #define icl__l3_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Gen11 L2Bank0 stalled metric set :: EU Thread Occupancy */ #define icl__l3_2__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Gen11 L2Bank1 stalled metric set :: GPU Core Clocks */ #define icl__l3_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gen11 L2Bank1 stalled metric set :: EU Active */ #define icl__l3_3__eu_active__read \ bdw__render_basic__eu_active__read /* Gen11 L2Bank1 stalled metric set :: EU Both FPU Pipes Active */ #define icl__l3_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Gen11 L2Bank1 stalled metric set :: VS Send Pipe Active */ #define icl__l3_3__vs_send_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Gen11 L2Bank1 stalled metric set :: VS FPU1 Pipe Active */ #define icl__l3_3__vs_fpu1_active__read \ bdw__render_basic__vs_send_active__read /* Gen11 L2Bank1 stalled metric set :: GS Threads Dispatched */ #define icl__l3_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Gen11 L2Bank1 stalled metric set :: Early Hi-Depth Test Fails */ #define icl__l3_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Gen11 L2Bank1 stalled metric set :: FS Both FPU Active */ #define icl__l3_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_send_active__read /* Gen11 L2Bank1 stalled metric set :: VS Threads Dispatched */ #define icl__l3_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Gen11 L2Bank1 stalled metric set :: Slice0 L3 Bank1 Stalled */ #define icl__l3_3__l30_bank1_stalled__read \ icl__l3_2__l30_bank0_stalled__read /* Gen11 L2Bank1 stalled metric set :: FS Threads Dispatched */ #define icl__l3_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Gen11 L2Bank1 stalled metric set :: Pixels Failing Tests */ #define icl__l3_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Gen11 L2Bank1 stalled metric set :: GPU Time Elapsed */ #define icl__l3_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gen11 L2Bank1 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gen11 L2Bank1 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gen11 L2Bank1 stalled metric set :: CS Threads Dispatched */ #define icl__l3_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Gen11 L2Bank1 stalled metric set :: PS FPU1 Pipe Active */ #define icl__l3_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu0_active__read /* Gen11 L2Bank1 stalled metric set :: PS Send Pipeline Active */ #define icl__l3_3__ps_send_active__read \ bdw__render_basic__ps_fpu1_active__read /* Gen11 L2Bank1 stalled metric set :: Rasterized Pixels */ #define icl__l3_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Gen11 L2Bank1 stalled metric set :: GPU Busy */ #define icl__l3_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gen11 L2Bank1 stalled metric set :: VS FPU0 Pipe Active */ #define icl__l3_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu1_active__read /* Gen11 L2Bank1 stalled metric set :: PS FPU0 Pipe Active */ #define icl__l3_3__ps_fpu0_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Gen11 L2Bank1 stalled metric set :: DS Threads Dispatched */ #define icl__l3_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Gen11 L2Bank1 stalled metric set :: Samples Written */ #define icl__l3_3__samples_written__read \ bdw__render_basic__samples_written__read /* Gen11 L2Bank1 stalled metric set :: EU Stall */ #define icl__l3_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Gen11 L2Bank1 stalled metric set :: Samples Blended */ #define icl__l3_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Gen11 L2Bank1 stalled metric set :: Early Depth Test Fails */ #define icl__l3_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Gen11 L2Bank1 stalled metric set :: HS Threads Dispatched */ #define icl__l3_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Gen11 L2Bank1 stalled metric set :: Samples Killed in FS */ #define icl__l3_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Gen11 L2Bank1 stalled metric set :: EU Thread Occupancy */ #define icl__l3_3__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Gen11 L2Bank4 stalled metric set :: GPU Core Clocks */ #define icl__l3_4__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gen11 L2Bank4 stalled metric set :: EU Active */ #define icl__l3_4__eu_active__read \ bdw__render_basic__eu_active__read /* Gen11 L2Bank4 stalled metric set :: EU Both FPU Pipes Active */ #define icl__l3_4__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Gen11 L2Bank4 stalled metric set :: VS Send Pipe Active */ #define icl__l3_4__vs_send_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Gen11 L2Bank4 stalled metric set :: VS FPU1 Pipe Active */ #define icl__l3_4__vs_fpu1_active__read \ bdw__render_basic__vs_send_active__read /* Gen11 L2Bank4 stalled metric set :: GS Threads Dispatched */ #define icl__l3_4__gs_threads__read \ hsw__render_basic__vs_threads__read /* Gen11 L2Bank4 stalled metric set :: Early Hi-Depth Test Fails */ #define icl__l3_4__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Gen11 L2Bank4 stalled metric set :: FS Both FPU Active */ #define icl__l3_4__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_send_active__read /* Gen11 L2Bank4 stalled metric set :: VS Threads Dispatched */ #define icl__l3_4__vs_threads__read \ bdw__render_basic__vs_threads__read /* Gen11 L2Bank4 stalled metric set :: FS Threads Dispatched */ #define icl__l3_4__ps_threads__read \ bdw__render_basic__ps_threads__read /* Gen11 L2Bank4 stalled metric set :: Pixels Failing Tests */ #define icl__l3_4__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Gen11 L2Bank4 stalled metric set :: GPU Time Elapsed */ #define icl__l3_4__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gen11 L2Bank4 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_4__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gen11 L2Bank4 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_4__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gen11 L2Bank4 stalled metric set :: CS Threads Dispatched */ #define icl__l3_4__cs_threads__read \ bdw__render_basic__cs_threads__read /* Gen11 L2Bank4 stalled metric set :: PS FPU1 Pipe Active */ #define icl__l3_4__ps_fpu1_active__read \ bdw__render_basic__ps_fpu0_active__read /* Gen11 L2Bank4 stalled metric set :: PS Send Pipeline Active */ #define icl__l3_4__ps_send_active__read \ bdw__render_basic__ps_fpu1_active__read /* Gen11 L2Bank4 stalled metric set :: Rasterized Pixels */ #define icl__l3_4__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Gen11 L2Bank4 stalled metric set :: GPU Busy */ #define icl__l3_4__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gen11 L2Bank4 stalled metric set :: VS FPU0 Pipe Active */ #define icl__l3_4__vs_fpu0_active__read \ bdw__render_basic__vs_fpu1_active__read /* Gen11 L2Bank4 stalled metric set :: PS FPU0 Pipe Active */ #define icl__l3_4__ps_fpu0_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Gen11 L2Bank4 stalled metric set :: DS Threads Dispatched */ #define icl__l3_4__ds_threads__read \ bdw__render_basic__ds_threads__read /* Gen11 L2Bank4 stalled metric set :: Samples Written */ #define icl__l3_4__samples_written__read \ bdw__render_basic__samples_written__read /* Gen11 L2Bank4 stalled metric set :: EU Stall */ #define icl__l3_4__eu_stall__read \ bdw__render_basic__eu_stall__read /* Gen11 L2Bank4 stalled metric set :: Samples Blended */ #define icl__l3_4__samples_blended__read \ bdw__render_basic__samples_blended__read /* Gen11 L2Bank4 stalled metric set :: Early Depth Test Fails */ #define icl__l3_4__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Gen11 L2Bank4 stalled metric set :: Slice0 L3 Bank4 Stalled */ #define icl__l3_4__l30_bank4_stalled__read \ icl__l3_2__l30_bank0_stalled__read /* Gen11 L2Bank4 stalled metric set :: HS Threads Dispatched */ #define icl__l3_4__hs_threads__read \ bdw__render_basic__hs_threads__read /* Gen11 L2Bank4 stalled metric set :: Samples Killed in FS */ #define icl__l3_4__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Gen11 L2Bank4 stalled metric set :: EU Thread Occupancy */ #define icl__l3_4__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Gen11 L2Bank5 stalled metric set :: GPU Core Clocks */ #define icl__l3_5__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gen11 L2Bank5 stalled metric set :: EU Active */ #define icl__l3_5__eu_active__read \ bdw__render_basic__eu_active__read /* Gen11 L2Bank5 stalled metric set :: EU Both FPU Pipes Active */ #define icl__l3_5__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Gen11 L2Bank5 stalled metric set :: VS Send Pipe Active */ #define icl__l3_5__vs_send_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Gen11 L2Bank5 stalled metric set :: VS FPU1 Pipe Active */ #define icl__l3_5__vs_fpu1_active__read \ bdw__render_basic__vs_send_active__read /* Gen11 L2Bank5 stalled metric set :: GS Threads Dispatched */ #define icl__l3_5__gs_threads__read \ hsw__render_basic__vs_threads__read /* Gen11 L2Bank5 stalled metric set :: Early Hi-Depth Test Fails */ #define icl__l3_5__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Gen11 L2Bank5 stalled metric set :: FS Both FPU Active */ #define icl__l3_5__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_send_active__read /* Gen11 L2Bank5 stalled metric set :: VS Threads Dispatched */ #define icl__l3_5__vs_threads__read \ bdw__render_basic__vs_threads__read /* Gen11 L2Bank5 stalled metric set :: FS Threads Dispatched */ #define icl__l3_5__ps_threads__read \ bdw__render_basic__ps_threads__read /* Gen11 L2Bank5 stalled metric set :: Pixels Failing Tests */ #define icl__l3_5__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Gen11 L2Bank5 stalled metric set :: GPU Time Elapsed */ #define icl__l3_5__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gen11 L2Bank5 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_5__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gen11 L2Bank5 stalled metric set :: AVG GPU Core Frequency */ #define icl__l3_5__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gen11 L2Bank5 stalled metric set :: CS Threads Dispatched */ #define icl__l3_5__cs_threads__read \ bdw__render_basic__cs_threads__read /* Gen11 L2Bank5 stalled metric set :: PS FPU1 Pipe Active */ #define icl__l3_5__ps_fpu1_active__read \ bdw__render_basic__ps_fpu0_active__read /* Gen11 L2Bank5 stalled metric set :: PS Send Pipeline Active */ #define icl__l3_5__ps_send_active__read \ bdw__render_basic__ps_fpu1_active__read /* Gen11 L2Bank5 stalled metric set :: Rasterized Pixels */ #define icl__l3_5__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Gen11 L2Bank5 stalled metric set :: GPU Busy */ #define icl__l3_5__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Gen11 L2Bank5 stalled metric set :: VS FPU0 Pipe Active */ #define icl__l3_5__vs_fpu0_active__read \ bdw__render_basic__vs_fpu1_active__read /* Gen11 L2Bank5 stalled metric set :: PS FPU0 Pipe Active */ #define icl__l3_5__ps_fpu0_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Gen11 L2Bank5 stalled metric set :: DS Threads Dispatched */ #define icl__l3_5__ds_threads__read \ bdw__render_basic__ds_threads__read /* Gen11 L2Bank5 stalled metric set :: Samples Written */ #define icl__l3_5__samples_written__read \ bdw__render_basic__samples_written__read /* Gen11 L2Bank5 stalled metric set :: EU Stall */ #define icl__l3_5__eu_stall__read \ bdw__render_basic__eu_stall__read /* Gen11 L2Bank5 stalled metric set :: Samples Blended */ #define icl__l3_5__samples_blended__read \ bdw__render_basic__samples_blended__read /* Gen11 L2Bank5 stalled metric set :: Early Depth Test Fails */ #define icl__l3_5__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Gen11 L2Bank5 stalled metric set :: HS Threads Dispatched */ #define icl__l3_5__hs_threads__read \ bdw__render_basic__hs_threads__read /* Gen11 L2Bank5 stalled metric set :: Samples Killed in FS */ #define icl__l3_5__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Gen11 L2Bank5 stalled metric set :: Slice0 L3 Bank5 Stalled */ static float icl__l3_5__l30_bank5_stalled__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: B 2 READ B 3 READ FADD B 0 READ FADD B 1 READ FADD 4 FDIV 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->b_offset + 2]; uint64_t tmp1 = accumulator[query->b_offset + 3]; double tmp2 = tmp0 + tmp1; uint64_t tmp3 = accumulator[query->b_offset + 0]; double tmp4 = tmp2 + tmp3; uint64_t tmp5 = accumulator[query->b_offset + 1]; double tmp6 = tmp4 + tmp5; double tmp7 = tmp6; double tmp8 = 4; double tmp9 = tmp8 ? tmp7 / tmp8 : 0; uint64_t tmp10 = tmp9 * 100; double tmp11 = tmp10; double tmp12 = icl__l3_5__gpu_core_clocks__read(perf, query, accumulator); double tmp13 = tmp12 ? tmp11 / tmp12 : 0; return tmp13; } /* Gen11 L2Bank5 stalled metric set :: EU Thread Occupancy */ #define icl__l3_5__eu_thread_occupancy__read \ bdw__vme_pipe__eu_thread_occupancy__read /* Metric set Sampler 1 :: GPU Core Clocks */ #define icl__sampler_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler 1 :: EU Active */ #define icl__sampler_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler 1 :: Slice0 Subslice2 Input Available */ #define icl__sampler_1__sampler02_input_available__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set Sampler 1 :: EU Both FPU Pipes Active */ #define icl__sampler_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler 1 :: VS Send Pipe Active */ #define icl__sampler_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler 1 :: Slice0 Subslice0 Input Available */ #define icl__sampler_1__sampler00_input_available__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set Sampler 1 :: VS FPU1 Pipe Active */ #define icl__sampler_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler 1 :: GS Threads Dispatched */ #define icl__sampler_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler 1 :: Early Hi-Depth Test Fails */ #define icl__sampler_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler 1 :: FS Both FPU Active */ #define icl__sampler_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler 1 :: VS Threads Dispatched */ #define icl__sampler_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler 1 :: FS Threads Dispatched */ #define icl__sampler_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler 1 :: Shader Barrier Messages */ #define icl__sampler_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler 1 :: Slice0 Subslice1 Input Available */ #define icl__sampler_1__sampler01_input_available__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Metric set Sampler 1 :: Sampler Texels */ #define icl__sampler_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler 1 :: Pixels Failing Tests */ #define icl__sampler_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler 1 :: Slice0 Subslice6 Input Available */ #define icl__sampler_1__sampler06_input_available__read \ bdw__render_basic__sampler1_busy__read /* Metric set Sampler 1 :: GPU Time Elapsed */ #define icl__sampler_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler 1 :: AVG GPU Core Frequency */ #define icl__sampler_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler 1 :: AVG GPU Core Frequency */ #define icl__sampler_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler 1 :: Sampler Texels Misses */ #define icl__sampler_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler 1 :: CS Threads Dispatched */ #define icl__sampler_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler 1 :: SLM Bytes Read */ #define icl__sampler_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler 1 :: Slice0 Subslice4 Input Available */ #define icl__sampler_1__sampler04_input_available__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set Sampler 1 :: PS FPU1 Pipe Active */ #define icl__sampler_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler 1 :: PS Send Pipeline Active */ #define icl__sampler_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler 1 :: VS FPU0 Pipe Active */ #define icl__sampler_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler 1 :: GPU Busy */ #define icl__sampler_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler 1 :: Rasterized Pixels */ #define icl__sampler_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler 1 :: Slice0 Subslice3 Input Available */ #define icl__sampler_1__sampler03_input_available__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set Sampler 1 :: PS FPU0 Pipe Active */ #define icl__sampler_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler 1 :: DS Threads Dispatched */ #define icl__sampler_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler 1 :: Samples Written */ #define icl__sampler_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler 1 :: EU Stall */ #define icl__sampler_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler 1 :: Slice0 Subslice5 Input Available */ #define icl__sampler_1__sampler05_input_available__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set Sampler 1 :: Samples Blended */ #define icl__sampler_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler 1 :: Early Depth Test Fails */ #define icl__sampler_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler 1 :: Slice0 Subslice7 Input Available */ #define icl__sampler_1__sampler07_input_available__read \ bdw__render_basic__sampler0_busy__read /* Metric set Sampler 1 :: Shader Memory Accesses */ #define icl__sampler_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler 1 :: HS Threads Dispatched */ #define icl__sampler_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler 1 :: L3 Shader Throughput */ #define icl__sampler_1__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set Sampler 1 :: Samples Killed in FS */ #define icl__sampler_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler 1 :: SLM Bytes Written */ #define icl__sampler_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler 1 :: Shader Atomic Memory Accesses */ #define icl__sampler_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set Sampler 2 :: GPU Core Clocks */ #define icl__sampler_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set Sampler 2 :: EU Active */ #define icl__sampler_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set Sampler 2 :: EU Both FPU Pipes Active */ #define icl__sampler_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set Sampler 2 :: SQ is full */ #define icl__sampler_2__gt_request_queue_full__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set Sampler 2 :: VS Send Pipe Active */ #define icl__sampler_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set Sampler 2 :: VS FPU1 Pipe Active */ #define icl__sampler_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set Sampler 2 :: GS Threads Dispatched */ #define icl__sampler_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set Sampler 2 :: Early Hi-Depth Test Fails */ #define icl__sampler_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set Sampler 2 :: FS Both FPU Active */ #define icl__sampler_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set Sampler 2 :: VS Threads Dispatched */ #define icl__sampler_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set Sampler 2 :: Slice0 Subslice2 Sampler Output Ready */ #define icl__sampler_2__sampler02_output_ready__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set Sampler 2 :: FS Threads Dispatched */ #define icl__sampler_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set Sampler 2 :: Slice0 Subslice6 Sampler Output Ready */ #define icl__sampler_2__sampler06_output_ready__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set Sampler 2 :: Slice0 Subslice4 Sampler Output Ready */ #define icl__sampler_2__sampler04_output_ready__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set Sampler 2 :: Shader Barrier Messages */ #define icl__sampler_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set Sampler 2 :: Sampler Texels */ #define icl__sampler_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set Sampler 2 :: Pixels Failing Tests */ #define icl__sampler_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set Sampler 2 :: Slice0 Subslice3 Sampler Output Ready */ #define icl__sampler_2__sampler03_output_ready__read \ bdw__render_pipe_profile__so_stall__read /* Metric set Sampler 2 :: GPU Time Elapsed */ #define icl__sampler_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set Sampler 2 :: AVG GPU Core Frequency */ #define icl__sampler_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set Sampler 2 :: AVG GPU Core Frequency */ #define icl__sampler_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set Sampler 2 :: Sampler Texels Misses */ #define icl__sampler_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set Sampler 2 :: CS Threads Dispatched */ #define icl__sampler_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set Sampler 2 :: SLM Bytes Read */ #define icl__sampler_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set Sampler 2 :: PS FPU1 Pipe Active */ #define icl__sampler_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set Sampler 2 :: PS Send Pipeline Active */ #define icl__sampler_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set Sampler 2 :: VS FPU0 Pipe Active */ #define icl__sampler_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set Sampler 2 :: GPU Busy */ #define icl__sampler_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set Sampler 2 :: Slice0 Subslice7 Sampler Output Ready */ #define icl__sampler_2__sampler07_output_ready__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set Sampler 2 :: Rasterized Pixels */ #define icl__sampler_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set Sampler 2 :: Slice0 Subslice5 Sampler Output Ready */ #define icl__sampler_2__sampler05_output_ready__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set Sampler 2 :: PS FPU0 Pipe Active */ #define icl__sampler_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set Sampler 2 :: DS Threads Dispatched */ #define icl__sampler_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set Sampler 2 :: Samples Written */ #define icl__sampler_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set Sampler 2 :: EU Stall */ #define icl__sampler_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set Sampler 2 :: Samples Blended */ #define icl__sampler_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set Sampler 2 :: Early Depth Test Fails */ #define icl__sampler_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set Sampler 2 :: Slice0 Subslice0 Sampler Output Ready */ #define icl__sampler_2__sampler00_output_ready__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Metric set Sampler 2 :: Slice0 Subslice1 Sampler Output Ready */ #define icl__sampler_2__sampler01_output_ready__read \ bdw__render_pipe_profile__hs_stall__read /* Metric set Sampler 2 :: Shader Memory Accesses */ #define icl__sampler_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set Sampler 2 :: HS Threads Dispatched */ #define icl__sampler_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set Sampler 2 :: L3 Shader Throughput */ #define icl__sampler_2__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set Sampler 2 :: Samples Killed in FS */ #define icl__sampler_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set Sampler 2 :: SLM Bytes Written */ #define icl__sampler_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set Sampler 2 :: Shader Atomic Memory Accesses */ #define icl__sampler_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: GPU Core Clocks */ #define icl__tdl_1__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_1 :: EU Active */ #define icl__tdl_1__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_1 :: EU Both FPU Pipes Active */ #define icl__tdl_1__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_1 :: VS Send Pipe Active */ #define icl__tdl_1__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_1 :: VS FPU1 Pipe Active */ #define icl__tdl_1__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_1 :: GS Threads Dispatched */ #define icl__tdl_1__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_1 :: Early Hi-Depth Test Fails */ #define icl__tdl_1__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_1 :: FS Both FPU Active */ #define icl__tdl_1__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_1 :: VS Threads Dispatched */ #define icl__tdl_1__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_1 :: FS Threads Dispatched */ #define icl__tdl_1__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_1 :: Samples Blended */ #define icl__tdl_1__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_1 :: Shader Barrier Messages */ #define icl__tdl_1__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher */ #define icl__tdl_1__ps_thread03_ready_for_dispatch__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_1 :: Sampler Texels */ #define icl__tdl_1__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_1 :: Pixels Failing Tests */ #define icl__tdl_1__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_1 :: GPU Time Elapsed */ #define icl__tdl_1__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define icl__tdl_1__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_1 :: AVG GPU Core Frequency */ #define icl__tdl_1__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_1 :: Sampler Texels Misses */ #define icl__tdl_1__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_1 :: CS Threads Dispatched */ #define icl__tdl_1__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_1 :: SLM Bytes Read */ #define icl__tdl_1__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_1 :: FS AVG Stall per Thread */ static uint64_t icl__tdl_1__ps_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 20 READ A 6 READ UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 20]; uint64_t tmp1 = accumulator[query->a_offset + 6]; uint64_t tmp2 = tmp0; uint64_t tmp3 = tmp1; uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Metric set TDL_1 :: PS FPU1 Pipe Active */ #define icl__tdl_1__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_1 :: VS AVG Stall per Thread */ static uint64_t icl__tdl_1__vs_eu_stall_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 14 READ A 1 READ UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 14]; uint64_t tmp1 = accumulator[query->a_offset + 1]; uint64_t tmp2 = tmp0; uint64_t tmp3 = tmp1; uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Metric set TDL_1 :: PS Send Pipeline Active */ #define icl__tdl_1__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_1 :: Rasterized Pixels */ #define icl__tdl_1__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_1 :: GPU Busy */ #define icl__tdl_1__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_1 :: FS AVG Active per Thread */ static uint64_t icl__tdl_1__ps_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 19 READ A 6 READ UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 19]; uint64_t tmp1 = accumulator[query->a_offset + 6]; uint64_t tmp2 = tmp0; uint64_t tmp3 = tmp1; uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Metric set TDL_1 :: FS EU Active */ #define icl__tdl_1__ps_eu_active__read \ bdw__compute_l3_cache__eu_move_fpu0_instruction__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */ #define icl__tdl_1__ps_thread00_ready_for_dispatch__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set TDL_1 :: Shader Atomic Memory Accesses */ #define icl__tdl_1__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_1 :: VS FPU0 Pipe Active */ #define icl__tdl_1__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher */ #define icl__tdl_1__ps_thread07_ready_for_dispatch__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_1 :: PS FPU0 Pipe Active */ #define icl__tdl_1__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_1 :: DS Threads Dispatched */ #define icl__tdl_1__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_1 :: FS EU Stall */ #define icl__tdl_1__ps_eu_stall__read \ bdw__compute_l3_cache__eu_move_fpu1_instruction__read /* Metric set TDL_1 :: EU Stall */ #define icl__tdl_1__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher */ #define icl__tdl_1__ps_thread05_ready_for_dispatch__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_1 :: VS EU Active */ #define icl__tdl_1__vs_eu_active__read \ bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read /* Metric set TDL_1 :: Early Depth Test Fails */ #define icl__tdl_1__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */ #define icl__tdl_1__ps_thread01_ready_for_dispatch__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher */ #define icl__tdl_1__ps_thread04_ready_for_dispatch__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_1 :: VS EU Stall */ #define icl__tdl_1__vs_eu_stall__read \ bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read /* Metric set TDL_1 :: Shader Memory Accesses */ #define icl__tdl_1__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_1 :: VS AVG Active per Thread */ static uint64_t icl__tdl_1__vs_eu_active_per_thread__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: A 13 READ A 1 READ UDIV */ uint64_t tmp0 = accumulator[query->a_offset + 13]; uint64_t tmp1 = accumulator[query->a_offset + 1]; uint64_t tmp2 = tmp0; uint64_t tmp3 = tmp1; uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; return tmp4; } /* Metric set TDL_1 :: HS Threads Dispatched */ #define icl__tdl_1__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */ #define icl__tdl_1__ps_thread02_ready_for_dispatch__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_1 :: L3 Shader Throughput */ #define icl__tdl_1__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set TDL_1 :: Samples Killed in FS */ #define icl__tdl_1__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_1 :: SLM Bytes Written */ #define icl__tdl_1__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_1 :: Samples Written */ #define icl__tdl_1__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher */ #define icl__tdl_1__ps_thread06_ready_for_dispatch__read \ bdw__render_basic__sampler1_busy__read /* Metric set TDL_2 :: GPU Core Clocks */ #define icl__tdl_2__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_2 :: EU Active */ #define icl__tdl_2__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_2 :: EU Both FPU Pipes Active */ #define icl__tdl_2__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_2 :: SQ is full */ #define icl__tdl_2__gt_request_queue_full__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_2 :: VS Send Pipe Active */ #define icl__tdl_2__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_2 :: VS FPU1 Pipe Active */ #define icl__tdl_2__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_2 :: GS Threads Dispatched */ #define icl__tdl_2__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_2 :: Early Hi-Depth Test Fails */ #define icl__tdl_2__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_2 :: FS Both FPU Active */ #define icl__tdl_2__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_2 :: VS Threads Dispatched */ #define icl__tdl_2__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_2 :: FS Threads Dispatched */ #define icl__tdl_2__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread02_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 1 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 1]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: Shader Barrier Messages */ #define icl__tdl_2__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread03_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 2 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 2]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: Sampler Texels */ #define icl__tdl_2__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_2 :: Pixels Failing Tests */ #define icl__tdl_2__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_2 :: GPU Time Elapsed */ #define icl__tdl_2__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define icl__tdl_2__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_2 :: AVG GPU Core Frequency */ #define icl__tdl_2__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_2 :: Sampler Texels Misses */ #define icl__tdl_2__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread00_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ B 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->b_offset + 7]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: CS Threads Dispatched */ #define icl__tdl_2__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_2 :: SLM Bytes Read */ #define icl__tdl_2__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_2 :: PS FPU1 Pipe Active */ #define icl__tdl_2__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_2 :: PS Send Pipeline Active */ #define icl__tdl_2__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_2 :: VS FPU0 Pipe Active */ #define icl__tdl_2__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_2 :: GPU Busy */ #define icl__tdl_2__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread07_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 6 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 6]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: Rasterized Pixels */ #define icl__tdl_2__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_2 :: PS FPU0 Pipe Active */ #define icl__tdl_2__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_2 :: DS Threads Dispatched */ #define icl__tdl_2__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_2 :: Samples Written */ #define icl__tdl_2__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_2 :: EU Stall */ #define icl__tdl_2__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_2 :: Samples Blended */ #define icl__tdl_2__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_2 :: Early Depth Test Fails */ #define icl__tdl_2__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread06_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 5 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 5]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: Shader Memory Accesses */ #define icl__tdl_2__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_2 :: HS Threads Dispatched */ #define icl__tdl_2__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread05_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 4 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 4]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread04_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 3]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_2 :: L3 Shader Throughput */ #define icl__tdl_2__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set TDL_2 :: Samples Killed in FS */ #define icl__tdl_2__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_2 :: SLM Bytes Written */ #define icl__tdl_2__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_2 :: Shader Atomic Memory Accesses */ #define icl__tdl_2__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */ static float icl__tdl_2__non_ps_thread01_ready_for_dispatch__read(MAYBE_UNUSED struct gen_perf *perf, const struct gen_perf_query_info *query, const uint64_t *accumulator) { /* RPN equation: GPU_CLOCK 0 READ C 0 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; uint64_t tmp1 = accumulator[query->c_offset + 0]; double tmp2 = tmp0 - tmp1; uint64_t tmp3 = tmp2 * 100; double tmp4 = tmp3; double tmp5 = icl__tdl_2__gpu_core_clocks__read(perf, query, accumulator); double tmp6 = tmp5 ? tmp4 / tmp5 : 0; return tmp6; } /* Metric set TDL_3 :: GPU Core Clocks */ #define icl__tdl_3__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TDL_3 :: EU Active */ #define icl__tdl_3__eu_active__read \ bdw__render_basic__eu_active__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header06_ready_port1__read \ bdw__render_pipe_profile__sf_stall__read /* Metric set TDL_3 :: EU Both FPU Pipes Active */ #define icl__tdl_3__eu_fpu_both_active__read \ bdw__render_basic__eu_fpu_both_active__read /* Metric set TDL_3 :: VS Send Pipe Active */ #define icl__tdl_3__vs_send_active__read \ bdw__render_basic__vs_send_active__read /* Metric set TDL_3 :: VS FPU1 Pipe Active */ #define icl__tdl_3__vs_fpu1_active__read \ bdw__render_basic__vs_fpu1_active__read /* Metric set TDL_3 :: GS Threads Dispatched */ #define icl__tdl_3__gs_threads__read \ hsw__render_basic__vs_threads__read /* Metric set TDL_3 :: Early Hi-Depth Test Fails */ #define icl__tdl_3__hi_depth_test_fails__read \ bdw__render_basic__hi_depth_test_fails__read /* Metric set TDL_3 :: FS Both FPU Active */ #define icl__tdl_3__ps_eu_both_fpu_active__read \ bdw__render_basic__ps_eu_both_fpu_active__read /* Metric set TDL_3 :: VS Threads Dispatched */ #define icl__tdl_3__vs_threads__read \ bdw__render_basic__vs_threads__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header03_ready_port0__read \ bdw__render_pipe_profile__sf_bottleneck__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header03_ready_port1__read \ bdw__render_pipe_profile__early_depth_bottleneck__read /* Metric set TDL_3 :: FS Threads Dispatched */ #define icl__tdl_3__ps_threads__read \ bdw__render_basic__ps_threads__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header04_ready_port1__read \ bdw__render_pipe_profile__hs_stall__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header04_ready_port0__read \ bdw__render_pipe_profile__vf_bottleneck__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header06_ready_port0__read \ bdw__render_pipe_profile__cl_stall__read /* Metric set TDL_3 :: Shader Barrier Messages */ #define icl__tdl_3__shader_barriers__read \ hsw__render_basic__early_depth_test_fails__read /* Metric set TDL_3 :: Sampler Texels */ #define icl__tdl_3__sampler_texels__read \ bdw__render_basic__sampler_texels__read /* Metric set TDL_3 :: Pixels Failing Tests */ #define icl__tdl_3__pixels_failing_post_ps_tests__read \ bdw__render_basic__pixels_failing_post_ps_tests__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header01_ready_port0__read \ bdw__render_basic__sampler0_bottleneck__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header01_ready_port1__read \ bdw__render_basic__sampler1_bottleneck__read /* Metric set TDL_3 :: GPU Time Elapsed */ #define icl__tdl_3__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TDL_3 :: AVG GPU Core Frequency */ #define icl__tdl_3__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TDL_3 :: AVG GPU Core Frequency */ #define icl__tdl_3__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TDL_3 :: Sampler Texels Misses */ #define icl__tdl_3__sampler_texel_misses__read \ bdw__render_basic__sampler_texel_misses__read /* Metric set TDL_3 :: CS Threads Dispatched */ #define icl__tdl_3__cs_threads__read \ bdw__render_basic__cs_threads__read /* Metric set TDL_3 :: SLM Bytes Read */ #define icl__tdl_3__slm_bytes_read__read \ bdw__render_basic__slm_bytes_read__read /* Metric set TDL_3 :: PS FPU1 Pipe Active */ #define icl__tdl_3__ps_fpu1_active__read \ bdw__render_basic__ps_fpu1_active__read /* Metric set TDL_3 :: PS Send Pipeline Active */ #define icl__tdl_3__ps_send_active__read \ bdw__render_basic__ps_send_active__read /* Metric set TDL_3 :: VS FPU0 Pipe Active */ #define icl__tdl_3__vs_fpu0_active__read \ bdw__render_basic__vs_fpu0_active__read /* Metric set TDL_3 :: GPU Busy */ #define icl__tdl_3__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header07_ready_port0__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header02_ready_port1__read \ bdw__render_pipe_profile__cl_bottleneck__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header02_ready_port0__read \ bdw__render_pipe_profile__so_bottleneck__read /* Metric set TDL_3 :: Rasterized Pixels */ #define icl__tdl_3__rasterized_pixels__read \ bdw__render_basic__rasterized_pixels__read /* Metric set TDL_3 :: PS FPU0 Pipe Active */ #define icl__tdl_3__ps_fpu0_active__read \ bdw__render_basic__ps_fpu0_active__read /* Metric set TDL_3 :: DS Threads Dispatched */ #define icl__tdl_3__ds_threads__read \ bdw__render_basic__ds_threads__read /* Metric set TDL_3 :: Samples Written */ #define icl__tdl_3__samples_written__read \ bdw__render_basic__samples_written__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header05_ready_port0__read \ bdw__render_pipe_profile__ds_stall__read /* Metric set TDL_3 :: EU Stall */ #define icl__tdl_3__eu_stall__read \ bdw__render_basic__eu_stall__read /* Metric set TDL_3 :: Samples Blended */ #define icl__tdl_3__samples_blended__read \ bdw__render_basic__samples_blended__read /* Metric set TDL_3 :: Early Depth Test Fails */ #define icl__tdl_3__early_depth_test_fails__read \ bdw__render_basic__early_depth_test_fails__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header07_ready_port1__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Metric set TDL_3 :: Shader Memory Accesses */ #define icl__tdl_3__shader_memory_accesses__read \ bdw__render_basic__shader_memory_accesses__read /* Metric set TDL_3 :: HS Threads Dispatched */ #define icl__tdl_3__hs_threads__read \ bdw__render_basic__hs_threads__read /* Metric set TDL_3 :: L3 Shader Throughput */ #define icl__tdl_3__l3_shader_throughput__read \ cnl__render_basic__l3_shader_throughput__read /* Metric set TDL_3 :: Samples Killed in FS */ #define icl__tdl_3__samples_killed_in_ps__read \ bdw__render_basic__samples_killed_in_ps__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header05_ready_port1__read \ bdw__render_pipe_profile__so_stall__read /* Metric set TDL_3 :: SLM Bytes Written */ #define icl__tdl_3__slm_bytes_written__read \ bdw__render_basic__slm_bytes_written__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0 */ #define icl__tdl_3__thread_header00_ready_port0__read \ bdw__render_basic__sampler0_busy__read /* Metric set TDL_3 :: Shader Atomic Memory Accesses */ #define icl__tdl_3__shader_atomics__read \ bdw__render_basic__shader_atomics__read /* Metric set TDL_3 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1 */ #define icl__tdl_3__thread_header00_ready_port1__read \ bdw__render_basic__sampler1_busy__read /* Gpu Rings Busyness :: GPU Core Clocks */ #define icl__gpu_busyness__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Gpu Rings Busyness :: Vebox Ring Busy */ #define icl__gpu_busyness__vebox_busy__read \ bdw__render_pipe_profile__cl_stall__read /* Gpu Rings Busyness :: GPU Time Elapsed */ #define icl__gpu_busyness__gpu_time__read \ hsw__render_basic__gpu_time__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define icl__gpu_busyness__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Gpu Rings Busyness :: AVG GPU Core Frequency */ #define icl__gpu_busyness__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Gpu Rings Busyness :: Render Ring Busy */ #define icl__gpu_busyness__render_busy__read \ bdw__render_pipe_profile__bc_bottleneck__read /* Gpu Rings Busyness :: Vdbox0 Ring Busy */ #define icl__gpu_busyness__vdbox0_busy__read \ bdw__render_pipe_profile__hi_depth_bottleneck__read /* Gpu Rings Busyness :: Posh Ring Busy */ #define icl__gpu_busyness__posh_engine_busy__read \ bdw__render_pipe_profile__ds_stall__read /* Gpu Rings Busyness :: Blitter Ring Busy */ #define icl__gpu_busyness__blitter_busy__read \ bdw__render_pipe_profile__so_stall__read /* Gpu Rings Busyness :: Vdbox1 Ring Busy */ #define icl__gpu_busyness__vdbox1_busy__read \ bdw__render_pipe_profile__sf_stall__read /* Gpu Rings Busyness :: AnyRingBusy */ #define icl__gpu_busyness__any_ring_busy__read \ bdw__render_basic__sampler0_busy__read /* Gpu Rings Busyness :: GPU Busy */ #define icl__gpu_busyness__gpu_busy__read \ bdw__render_basic__gpu_busy__read /* Metric set TestOa :: TestCounter7 */ #define icl__test_oa__counter7__read \ hsw__compute_extended__gpu_clocks__read /* Metric set TestOa :: GPU Time Elapsed */ #define icl__test_oa__gpu_time__read \ hsw__render_basic__gpu_time__read /* Metric set TestOa :: GPU Core Clocks */ #define icl__test_oa__gpu_core_clocks__read \ bdw__render_basic__gpu_core_clocks__read /* Metric set TestOa :: AVG GPU Core Frequency */ #define icl__test_oa__avg_gpu_core_frequency__read \ bdw__render_basic__avg_gpu_core_frequency__read /* Metric set TestOa :: AVG GPU Core Frequency */ #define icl__test_oa__avg_gpu_core_frequency__max \ hsw__render_basic__avg_gpu_core_frequency__max /* Metric set TestOa :: TestCounter8 */ #define icl__test_oa__counter8__read \ hsw__compute_extended__typed_writes0__read /* Metric set TestOa :: TestCounter4 */ #define icl__test_oa__counter4__read \ hsw__compute_extended__eu_untyped_atomics0__read /* Metric set TestOa :: TestCounter5 */ #define icl__test_oa__counter5__read \ hsw__compute_extended__eu_typed_atomics0__read /* Metric set TestOa :: TestCounter6 */ #define icl__test_oa__counter6__read \ hsw__compute_extended__eu_urb_atomics0__read /* Metric set TestOa :: TestCounter3 */ #define icl__test_oa__counter3__read \ hsw__compute_extended__eu_typed_writes0__read /* Metric set TestOa :: TestCounter0 */ #define icl__test_oa__counter0__read \ hsw__compute_extended__eu_untyped_reads0__read /* Metric set TestOa :: TestCounter1 */ #define icl__test_oa__counter1__read \ hsw__compute_extended__eu_untyped_writes0__read /* Metric set TestOa :: TestCounter2 */ #define icl__test_oa__counter2__read \ hsw__compute_extended__eu_typed_reads0__read static struct gen_perf_query_register_prog hsw_render_basic_mux_regs[60]; static struct gen_perf_query_register_prog hsw_render_basic_b_counter_regs[4]; static struct gen_perf_query_counter hsw_render_basic_query_counters[67]; static struct gen_perf_query_info hsw_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen7.5", .guid = "403d8832-1a27-4aa6-a64e-f5389ce7b212", .counters = hsw_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A45_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .a_offset = 1, .b_offset = 46, .c_offset = 54, .mux_regs = hsw_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = hsw_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void hsw_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &hsw_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x01600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025440, .val = 0x00100000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025128, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002691C, .val = 0x00000800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026AA0, .val = 0x01500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B9C, .val = 0x00006000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002791C, .val = 0x00000800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027AA0, .val = 0x01500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B9C, .val = 0x00006000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002641C, .val = 0x00000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002538C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025384, .val = 0x0800AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025400, .val = 0x00000004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002540C, .val = 0x06029000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025410, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025404, .val = 0x5C30FFFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025100, .val = 0x00000016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025110, .val = 0x00000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025104, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026804, .val = 0x00001211 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026884, .val = 0x00000100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026900, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026908, .val = 0x00700000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026904, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026984, .val = 0x00001022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026A04, .val = 0x00000011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026A80, .val = 0x00000006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026A88, .val = 0x00000C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026A84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B04, .val = 0x00001000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B80, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B8C, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027804, .val = 0x00004844 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027884, .val = 0x00000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027900, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027908, .val = 0x0E000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027904, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027984, .val = 0x00004088 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027A04, .val = 0x00000044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027A80, .val = 0x00000006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027A88, .val = 0x00018040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027A84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B04, .val = 0x00004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B80, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B8C, .val = 0x000000E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026104, .val = 0x00002222 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026184, .val = 0x0C006666 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026284, .val = 0x04000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026304, .val = 0x04000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026400, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026410, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026404, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025420, .val = 0x04108020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025424, .val = 0x1284A420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00042049 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__ds_eu_stall__read; counter->name = "TES EU Stall"; counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__alpha_test_fails__read; counter->name = "Alpha Test Fails"; counter->desc = "The total number of pixels dropped on post-FS alpha test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which sampler 1 was bottlenecks."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ds_threads__read; counter->name = "TES Threads Dispatched"; counter->desc = "The total number of evaluation shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ds_eu_active_per_thread__read; counter->name = "TES AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__gs_eu_stall__read; counter->name = "GS EU Stall"; counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__cs_eu_active__read; counter->name = "CS EU Active"; counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__vs_eu_active__read; counter->name = "VS EU Active"; counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__hs_eu_active__read; counter->name = "TCS EU Active"; counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 68; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__ds_eu_active__read; counter->name = "TES EU Active"; counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__gs_eu_active__read; counter->name = "GS EU Active"; counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 76; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__ps_eu_active__read; counter->name = "FS EU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__cs_eu_stall__read; counter->name = "CS EU Stall"; counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__vs_eu_stall__read; counter->name = "VS EU Stall"; counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__hs_eu_stall__read; counter->name = "TCS EU Stall"; counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__ps_eu_stall__read; counter->name = "FS EU Stall"; counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__cs_duration__read; counter->name = "CS Duration"; counter->desc = "Total Compute Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which sampler 0 was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which sampler 1 was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers were busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ds_duration__read; counter->name = "TES Duration"; counter->desc = "Total Evaluation Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__cs_eu_active_per_thread__read; counter->name = "CS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 184; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which sampler 0 was bottlenecks."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gs_eu_stall_per_thread__read; counter->name = "GS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__sampler0_texels__read; counter->name = "Sampler 0 Texels LOD0"; counter->desc = "The total number of texels lookups in LOD0 in sampler 0 unit."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__sampler1_texels__read; counter->name = "Sampler 1 Texels LOD0"; counter->desc = "The total number of texels lookups in LOD0 in sampler 1 unit."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__sampler_texels__read; counter->name = "Sampler Texels LOD0"; counter->desc = "The total number of texels lookups in LOD0 in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gs_duration__read; counter->name = "GS Duration"; counter->desc = "Total Geometry Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = hsw__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__eu_idle__read; counter->name = "EU Idle"; counter->desc = "The percentage of time in which the Execution Units were idle."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ps_eu_stall_per_thread__read; counter->name = "FS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__vs_eu_stall_per_thread__read; counter->name = "VS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ps_eu_active_per_thread__read; counter->name = "FS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__hs_duration__read; counter->name = "TCS Duration"; counter->desc = "Total Control Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ds_eu_stall_per_thread__read; counter->name = "TES AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gs_eu_active_per_thread__read; counter->name = "GS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__hs_threads__read; counter->name = "TCS Threads Dispatched"; counter->desc = "The total number of control shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__hs_eu_stall_per_thread__read; counter->name = "TCS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__post_ps_depth_test_fails__read; counter->name = "Late Depth Test Fails"; counter->desc = "The total number of pixels dropped on post-FS depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__render_basic__sampler_bottleneck__read; counter->name = "Sampler Bottleneck"; counter->desc = "The percentage of time in which samplers were bottlenecks."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__hs_eu_active_per_thread__read; counter->name = "TCS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 392; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__ps_duration__read; counter->name = "FS Duration"; counter->desc = "Total Fragment Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 400; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 408; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__cs_eu_stall_per_thread__read; counter->name = "CS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 416; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__post_ps_stencil_test_fails__read; counter->name = "Late Stencil Test Fails"; counter->desc = "The total number of pixels dropped on post-FS stencil test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 424; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 432; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 440; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__vs_eu_active_per_thread__read; counter->name = "VS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 448; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__vs_duration__read; counter->name = "VS Duration"; counter->desc = "Total Vertex Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 456; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 464; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog hsw_compute_basic_mux_regs[33]; static struct gen_perf_query_register_prog hsw_compute_basic_b_counter_regs[16]; static struct gen_perf_query_counter hsw_compute_basic_query_counters[50]; static struct gen_perf_query_info hsw_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen7.5", .guid = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", .counters = hsw_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A45_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .a_offset = 1, .b_offset = 46, .c_offset = 54, .mux_regs = hsw_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = hsw_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void hsw_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &hsw_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002681C, .val = 0x01F00800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026820, .val = 0x00001000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002781C, .val = 0x01F00800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026520, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000265A0, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002538C, .val = 0x00300000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025384, .val = 0xAA8AAAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFFFFFFFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026800, .val = 0x00004202 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026808, .val = 0x00605817 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002680C, .val = 0x10001005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026804, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027800, .val = 0x00000102 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027808, .val = 0x0C0701E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002780C, .val = 0x000200A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027804, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026484, .val = 0x44000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026704, .val = 0x44000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026500, .val = 0x00000006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026510, .val = 0x00000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026504, .val = 0x88000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026580, .val = 0x00000006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026590, .val = 0x00000020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026584, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026104, .val = 0x55822222 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026184, .val = 0xAA866666 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025420, .val = 0x08320C83 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025424, .val = 0x06820C83 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000C03 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xAAAAAAAA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xAAAAAAAA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xAAAAAAAA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xAAAAAAAA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x00000000 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__ds_eu_stall__read; counter->name = "TES EU Stall"; counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__alpha_test_fails__read; counter->name = "Alpha Test Fails"; counter->desc = "The total number of pixels dropped on post-FS alpha test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__hs_threads__read; counter->name = "TCS Threads Dispatched"; counter->desc = "The total number of control shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__hs_eu_active_per_thread__read; counter->name = "TCS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__gs_eu_stall__read; counter->name = "GS EU Stall"; counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__cs_eu_active_per_thread__read; counter->name = "CS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__gs_eu_stall_per_thread__read; counter->name = "GS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__typed_atomics__read; counter->name = "Typed Atomics"; counter->desc = "The total number of typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = hsw__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__ps_eu_stall_per_thread__read; counter->name = "FS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__ds_eu_active__read; counter->name = "TES EU Active"; counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__vs_eu_stall_per_thread__read; counter->name = "VS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__hs_eu_stall__read; counter->name = "TCS EU Stall"; counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__ps_eu_active_per_thread__read; counter->name = "FS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__ds_threads__read; counter->name = "TES Threads Dispatched"; counter->desc = "The total number of evaluation shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__ds_eu_active_per_thread__read; counter->name = "TES AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__gs_eu_active__read; counter->name = "GS EU Active"; counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__ps_eu_active__read; counter->name = "FS EU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__ds_eu_stall_per_thread__read; counter->name = "TES AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__gs_eu_active_per_thread__read; counter->name = "GS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of byten written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__hs_eu_stall_per_thread__read; counter->name = "TCS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__hs_eu_active__read; counter->name = "TCS EU Active"; counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__post_ps_depth_test_fails__read; counter->name = "Late Depth Test Fails"; counter->desc = "The total number of pixels dropped on post-FS depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__ps_eu_stall__read; counter->name = "FS EU Stall"; counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 284; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__vs_eu_active__read; counter->name = "VS EU Active"; counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__cs_eu_active__read; counter->name = "CS EU Active"; counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__cs_eu_stall_per_thread__read; counter->name = "CS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__post_ps_stencil_test_fails__read; counter->name = "Late Stencil Test Fails"; counter->desc = "The total number of pixels dropped on post-FS stencil test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__vs_eu_active_per_thread__read; counter->name = "VS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__cs_eu_stall__read; counter->name = "CS EU Stall"; counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_basic__vs_eu_stall__read; counter->name = "VS EU Stall"; counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 352; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog hsw_compute_extended_mux_regs[16]; static struct gen_perf_query_register_prog hsw_compute_extended_b_counter_regs[20]; static struct gen_perf_query_counter hsw_compute_extended_query_counters[20]; static struct gen_perf_query_info hsw_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen7.5", .guid = "3865be28-6982-49fe-9494-e4d1b4795413", .counters = hsw_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A45_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .a_offset = 1, .b_offset = 46, .c_offset = 54, .mux_regs = hsw_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = hsw_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void hsw_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &hsw_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002681C, .val = 0x3EB00800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026820, .val = 0x00900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025384, .val = 0x02AAAAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025404, .val = 0x03FFFFFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026800, .val = 0x00142284 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026808, .val = 0x0E629062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002680C, .val = 0x3F6F55CB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026810, .val = 0x00000014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026804, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026104, .val = 0x02AAAAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026184, .val = 0x02AAAAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025420, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FE2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FE92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FEA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FE32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FE9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FF23 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFFE }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__gpu_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__eu_urb_atomics0__read; counter->name = "EuUrbAtomics0"; counter->desc = "The subslice 0 EU URB Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog hsw_memory_reads_mux_regs[19]; static struct gen_perf_query_register_prog hsw_memory_reads_b_counter_regs[28]; static struct gen_perf_query_counter hsw_memory_reads_query_counters[54]; static struct gen_perf_query_info hsw_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen7.5", .guid = "bb5ed49b-2497-4095-94f6-26ba294db88a", .counters = hsw_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A45_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .a_offset = 1, .b_offset = 46, .c_offset = 54, .mux_regs = hsw_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = hsw_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void hsw_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &hsw_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x34300000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025440, .val = 0x2D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025444, .val = 0x00000008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025128, .val = 0x0E600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000450 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025390, .val = 0x00052C43 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025384, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025400, .val = 0x00006144 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025408, .val = 0x0A418820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002540C, .val = 0x000820E6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFF500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025100, .val = 0x000005D6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002510C, .val = 0x0EF00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025104, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025420, .val = 0x02108421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00008421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x76543298 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x98989898 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x000000E4 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x98A98A98 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x88888888 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x000C5500 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FC00 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__ds_eu_stall__read; counter->name = "TES EU Stall"; counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__alpha_test_fails__read; counter->name = "Alpha Test Fails"; counter->desc = "The total number of pixels dropped on post-FS alpha test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__ds_threads__read; counter->name = "TES Threads Dispatched"; counter->desc = "The total number of evaluation shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__ds_eu_active_per_thread__read; counter->name = "TES AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__gs_eu_stall__read; counter->name = "GS EU Stall"; counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__llc_read_accesses__read; counter->name = "LLC GPU Read Accesses"; counter->desc = "The total number of LLC cache lookups for reads done from the GPU."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads (64B each)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__cs_eu_active_per_thread__read; counter->name = "CS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gs_eu_stall_per_thread__read; counter->name = "GS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = hsw__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__ps_eu_stall_per_thread__read; counter->name = "FS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__ds_eu_active__read; counter->name = "TES EU Active"; counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__vs_eu_stall_per_thread__read; counter->name = "VS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__hs_eu_stall__read; counter->name = "TCS EU Stall"; counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__ps_eu_active_per_thread__read; counter->name = "FS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__gs_eu_active__read; counter->name = "GS EU Active"; counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__ps_eu_active__read; counter->name = "FS EU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__ds_eu_stall_per_thread__read; counter->name = "TES AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gs_eu_active_per_thread__read; counter->name = "GS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_hi_depth_memory_reads__read; counter->name = "GtiHiDepthMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__hs_threads__read; counter->name = "TCS Threads Dispatched"; counter->desc = "The total number of control shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__hs_eu_stall_per_thread__read; counter->name = "TCS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__hs_eu_active__read; counter->name = "TCS EU Active"; counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__post_ps_depth_test_fails__read; counter->name = "Late Depth Test Fails"; counter->desc = "The total number of pixels dropped on post-FS depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__hs_eu_active_per_thread__read; counter->name = "TCS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__ps_eu_stall__read; counter->name = "FS EU Stall"; counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 284; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__vs_eu_active__read; counter->name = "VS EU Active"; counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__cs_eu_active__read; counter->name = "CS EU Active"; counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 308; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__cs_eu_stall_per_thread__read; counter->name = "CS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__post_ps_stencil_test_fails__read; counter->name = "Late Stencil Test Fails"; counter->desc = "The total number of pixels dropped on post-FS stencil test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__vs_eu_active_per_thread__read; counter->name = "VS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__cs_eu_stall__read; counter->name = "CS EU Stall"; counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_reads__vs_eu_stall__read; counter->name = "VS EU Stall"; counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog hsw_memory_writes_mux_regs[19]; static struct gen_perf_query_register_prog hsw_memory_writes_b_counter_regs[28]; static struct gen_perf_query_counter hsw_memory_writes_query_counters[53]; static struct gen_perf_query_info hsw_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen7.5", .guid = "3358d639-9b5f-45ab-976d-9b08cbfc6240", .counters = hsw_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A45_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .a_offset = 1, .b_offset = 46, .c_offset = 54, .mux_regs = hsw_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = hsw_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void hsw_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &hsw_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x34300000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025440, .val = 0x01500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025444, .val = 0x00000120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025128, .val = 0x0C200000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000450 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025390, .val = 0x00052C43 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025384, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025400, .val = 0x00007184 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025408, .val = 0x0A418820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002540C, .val = 0x000820E6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFF500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025100, .val = 0x000005D6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002510C, .val = 0x1E700000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025104, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025420, .val = 0x02108421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00008421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x76543298 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x98989898 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x000000E4 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0xBABABABA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x88888888 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x000C5500 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FC00 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__ds_eu_stall__read; counter->name = "TES EU Stall"; counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__alpha_test_fails__read; counter->name = "Alpha Test Fails"; counter->desc = "The total number of pixels dropped on post-FS alpha test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__ds_threads__read; counter->name = "TES Threads Dispatched"; counter->desc = "The total number of evaluation shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__ds_eu_active_per_thread__read; counter->name = "TES AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__gs_eu_stall__read; counter->name = "GS EU Stall"; counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__cs_eu_active_per_thread__read; counter->name = "CS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gs_eu_stall_per_thread__read; counter->name = "GS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = hsw__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__ps_eu_stall_per_thread__read; counter->name = "FS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__ds_eu_active__read; counter->name = "TES EU Active"; counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__vs_eu_stall_per_thread__read; counter->name = "VS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__hs_eu_stall__read; counter->name = "TCS EU Stall"; counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__ps_eu_active_per_thread__read; counter->name = "FS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__llc_wr_accesses__read; counter->name = "LLC GPU Write Accesses"; counter->desc = "The total number of LLC cache lookups for write done from the GPU (32B writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__gs_eu_active__read; counter->name = "GS EU Active"; counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__ps_eu_active__read; counter->name = "FS EU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__ds_eu_stall_per_thread__read; counter->name = "TES AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gs_eu_active_per_thread__read; counter->name = "GS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__hs_threads__read; counter->name = "TCS Threads Dispatched"; counter->desc = "The total number of control shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__hs_eu_stall_per_thread__read; counter->name = "TCS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__hs_eu_active__read; counter->name = "TCS EU Active"; counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__post_ps_depth_test_fails__read; counter->name = "Late Depth Test Fails"; counter->desc = "The total number of pixels dropped on post-FS depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__hs_eu_active_per_thread__read; counter->name = "TCS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__ps_eu_stall__read; counter->name = "FS EU Stall"; counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 292; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__vs_eu_active__read; counter->name = "VS EU Active"; counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__cs_eu_active__read; counter->name = "CS EU Active"; counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 308; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__cs_eu_stall_per_thread__read; counter->name = "CS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__post_ps_stencil_test_fails__read; counter->name = "Late Stencil Test Fails"; counter->desc = "The total number of pixels dropped on post-FS stencil test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__vs_eu_active_per_thread__read; counter->name = "VS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__cs_eu_stall__read; counter->name = "CS EU Stall"; counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes (64B each)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__memory_writes__vs_eu_stall__read; counter->name = "VS EU Stall"; counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog hsw_sampler_balance_mux_regs[41]; static struct gen_perf_query_register_prog hsw_sampler_balance_b_counter_regs[6]; static struct gen_perf_query_counter hsw_sampler_balance_query_counters[55]; static struct gen_perf_query_info hsw_sampler_balance_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set SamplerBalance", .guid = "bc274488-b4b6-40c7-90da-b77d7ad16189", .counters = hsw_sampler_balance_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A45_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .a_offset = 1, .b_offset = 46, .c_offset = 54, .mux_regs = hsw_sampler_balance_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = hsw_sampler_balance_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void hsw_register_sampler_balance_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &hsw_sampler_balance_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002EB9C, .val = 0x01906400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002FB9C, .val = 0x01906400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B9C, .val = 0x01906400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B9C, .val = 0x01906400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027104, .val = 0x00A00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027184, .val = 0x00A50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002E804, .val = 0x00500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002E984, .val = 0x00500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002EB04, .val = 0x00500000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002EB80, .val = 0x00000084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002EB8C, .val = 0x14200000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002EB84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002F804, .val = 0x00050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002F984, .val = 0x00050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002FB04, .val = 0x00050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002FB80, .val = 0x00000084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002FB8C, .val = 0x00050800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002FB84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002538C, .val = 0x000000C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025384, .val = 0xAA550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFFFFC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026804, .val = 0x50000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026984, .val = 0x50000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B04, .val = 0x50000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B80, .val = 0x00000084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B90, .val = 0x00050800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026B84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027804, .val = 0x05000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027984, .val = 0x05000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B04, .val = 0x05000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B80, .val = 0x00000084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B90, .val = 0x00000142 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00027B84, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026104, .val = 0xA0000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00026184, .val = 0xA5000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00008620 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00025428, .val = 0x0004A54A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__ds_eu_stall__read; counter->name = "TES EU Stall"; counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler3_l2_cache_misses__read; counter->name = "Sampler L2 cache misses (ss3)"; counter->desc = "Number of sampler L2 cache misses (ss3)"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__alpha_test_fails__read; counter->name = "Alpha Test Fails"; counter->desc = "The total number of pixels dropped on post-FS alpha test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_threads__read; counter->name = "TES Threads Dispatched"; counter->desc = "The total number of evaluation shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_eu_active_per_thread__read; counter->name = "TES AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__gs_eu_stall__read; counter->name = "GS EU Stall"; counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__cs_eu_active__read; counter->name = "CS EU Active"; counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__vs_eu_active__read; counter->name = "VS EU Active"; counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__hs_eu_active__read; counter->name = "TCS EU Active"; counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 68; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__ds_eu_active__read; counter->name = "TES EU Active"; counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__gs_eu_active__read; counter->name = "GS EU Active"; counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 76; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__ps_eu_active__read; counter->name = "FS EU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__cs_eu_stall__read; counter->name = "CS EU Stall"; counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__vs_eu_stall__read; counter->name = "VS EU Stall"; counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__hs_eu_stall__read; counter->name = "TCS EU Stall"; counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__ps_eu_stall__read; counter->name = "FS EU Stall"; counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_duration__read; counter->name = "CS Duration"; counter->desc = "Total Compute Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_duration__read; counter->name = "TES Duration"; counter->desc = "Total Evaluation Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_duration__read; counter->name = "GS Duration"; counter->desc = "Total Geometry Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_eu_active_per_thread__read; counter->name = "CS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler_l2_cache_misses__read; counter->name = "Sampler L2 cache misses"; counter->desc = "Number of sampler L2 cache misses"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_eu_stall_per_thread__read; counter->name = "GS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler2_l2_cache_misses__read; counter->name = "Sampler L2 cache misses (ss2)"; counter->desc = "Number of sampler L2 cache misses (ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = hsw__sampler_balance__avg_gpu_core_frequency__max(perf); counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__eu_idle__read; counter->name = "EU Idle"; counter->desc = "The percentage of time in which the Execution Units were idle."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_eu_stall_per_thread__read; counter->name = "FS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_eu_stall_per_thread__read; counter->name = "VS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = hsw__sampler_balance__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_eu_active_per_thread__read; counter->name = "FS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_duration__read; counter->name = "TCS Duration"; counter->desc = "Total Control Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_eu_stall_per_thread__read; counter->name = "TES AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_eu_active_per_thread__read; counter->name = "GS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_threads__read; counter->name = "TCS Threads Dispatched"; counter->desc = "The total number of control shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_eu_stall_per_thread__read; counter->name = "TCS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__post_ps_depth_test_fails__read; counter->name = "Late Depth Test Fails"; counter->desc = "The total number of pixels dropped on post-FS depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_eu_active_per_thread__read; counter->name = "TCS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_duration__read; counter->name = "FS Duration"; counter->desc = "Total Fragment Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler1_l2_cache_misses__read; counter->name = "Sampler L2 cache misses (ss1)"; counter->desc = "Number of sampler L2 cache misses (ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_eu_stall_per_thread__read; counter->name = "CS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__post_ps_stencil_test_fails__read; counter->name = "Late Stencil Test Fails"; counter->desc = "The total number of pixels dropped on post-FS stencil test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler0_l2_cache_misses__read; counter->name = "Sampler L2 cache misses (ss0)"; counter->desc = "Number of sampler L2 cache misses (ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 352; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_eu_active_per_thread__read; counter->name = "VS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 100.0; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_duration__read; counter->name = "VS Duration"; counter->desc = "Total Vertex Shader GPU duration."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = hsw__sampler_balance__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_hsw(struct gen_perf *perf) { hsw_register_render_basic_counter_query(perf); hsw_register_compute_basic_counter_query(perf); hsw_register_compute_extended_counter_query(perf); hsw_register_memory_reads_counter_query(perf); hsw_register_memory_writes_counter_query(perf); hsw_register_sampler_balance_counter_query(perf); } static struct gen_perf_query_register_prog bdw_render_basic_mux_regs[219]; static struct gen_perf_query_register_prog bdw_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog bdw_render_basic_flex_regs[7]; static struct gen_perf_query_counter bdw_render_basic_query_counters[52]; static struct gen_perf_query_info bdw_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen8", .guid = "b541bd57-0e0f-4154-b4c0-5858010a2bf7", .counters = bdw_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.slice_mask & 0x01) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14110014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14310014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A0317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13837BE0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3F0023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18380001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08110031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06311800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08311880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10310000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16330080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABF1180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A0380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B2550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D831021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F83572F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01835680 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0383002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C137 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C147 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801110 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800331 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45801465 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53801111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478014A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800CA5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.slice_mask & 0x02) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14910014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B10014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A0317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13837BE0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3F0023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BD0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABF1180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B80001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00910030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08910031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10910000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16930020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B11800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B11880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B10000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B30080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88B800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A0380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B26A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D831021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F83572F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01835680 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0383002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C137 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C147 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800331 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x458004A1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53805555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800845 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_compute_basic_mux_regs[182]; static struct gen_perf_query_register_prog bdw_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog bdw_compute_basic_flex_regs[7]; static struct gen_perf_query_counter bdw_compute_basic_query_counters[39]; static struct gen_perf_query_info bdw_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen8", .guid = "35fbc9b2-a891-40a6-a38d-022bb7057552", .counters = bdw_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.slice_mask & 0x01) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C2100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C6580 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00580042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08582080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C58004C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E582580 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0104 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A382080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38404C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0238404B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381145 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808137 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C147 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C0E5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C0E3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.slice_mask & 0x02) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC2100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADC0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC6580 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D80042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D82080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8004C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED82580 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0104 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B80042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB82080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB8404C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B8404B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B81145 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808137 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C147 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C0E5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C0E3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D805000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of typed memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_render_pipe_profile_mux_regs[111]; static struct gen_perf_query_register_prog bdw_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog bdw_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter bdw_render_pipe_profile_query_counters[44]; static struct gen_perf_query_info bdw_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile", .guid = "233d0544-fff7-4281-8291-e02f222aff72", .counters = bdw_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10176800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1191001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B880320 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01890C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118D7C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118E0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118F4C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081E0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C13C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06164000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06170012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01910005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07880002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01880C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09890032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B54C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAA55 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8D0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8D3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8E0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198F0C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B900980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03900D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F801011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51801111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53801111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_memory_reads_mux_regs[50]; static struct gen_perf_query_register_prog bdw_memory_reads_b_counter_regs[28]; static struct gen_perf_query_register_prog bdw_memory_reads_flex_regs[7]; static struct gen_perf_query_counter bdw_memory_reads_query_counters[42]; static struct gen_perf_query_info bdw_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen8", .guid = "2b255d48-2117-4fef-a8f7-f151e1d25a2c", .counters = bdw_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0343 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13845800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15840018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B6B62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85A080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01840018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844C80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09840D9A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840E9C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D840F9E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F840010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F8000E5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138080E3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C0E1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_memory_writes_mux_regs[49]; static struct gen_perf_query_register_prog bdw_memory_writes_b_counter_regs[28]; static struct gen_perf_query_register_prog bdw_memory_writes_flex_regs[7]; static struct gen_perf_query_counter bdw_memory_writes_query_counters[41]; static struct gen_perf_query_info bdw_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen8", .guid = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c", .counters = bdw_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0343 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13845400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800805 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B6B62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85A080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23850002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01840010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09840992 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840A94 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D840B96 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D800147 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F8000E5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138080E3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C0E1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801082 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_compute_extended_mux_regs[648]; static struct gen_perf_query_register_prog bdw_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog bdw_compute_extended_flex_regs[7]; static struct gen_perf_query_counter bdw_compute_extended_query_counters[38]; static struct gen_perf_query_info bdw_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen8", .guid = "e99ccaca-821c-4df9-97a7-96bdb7204e43", .counters = bdw_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.subslice_mask & 0x01) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143D0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163D2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063D0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043D21B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5825C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00586100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258204C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C58C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0458C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5551 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.subslice_mask & 0x02) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145B0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165B2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C25C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C6100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C204C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B21B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5551 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.subslice_mask & 0x04) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183A0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38A5C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0038A100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0238204C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183802AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083A0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3A0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A21B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5551 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.subslice_mask & 0x08) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BD0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16BD2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BD0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BD0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BD0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BD0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABD0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBD2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BD21B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BD0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBD0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED825C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D86100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D8204C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B81555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.subslice_mask & 0x10) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14DB0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16DB2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC25C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC6100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DC204C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDB2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB21B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DB0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B81555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.subslice_mask & 0x20) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BA0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16BA2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BA0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB8A5C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B8A100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B8204C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B802AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BA0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BA0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BA0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BA21B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "Ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "Ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "Ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "Ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "Ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_compute_l3_cache_mux_regs[107]; static struct gen_perf_query_register_prog bdw_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog bdw_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter bdw_compute_l3_cache_query_counters[58]; static struct gen_perf_query_info bdw_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen8", .guid = "27a364dc-8225-4ecb-b607-d6f1925598d9", .counters = bdw_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F00B3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF00B3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138303C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800805 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0029 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063F1400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083F1225 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3F1327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABF1429 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF1225 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BF1380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF0026 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B91000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F880003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0520 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BA950 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03835180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C137 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C147 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x02) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank10_accesses__read; counter->name = "L3 Bank 10 Accesses"; counter->desc = "The total number of accesses to L3 Bank 10."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; if (perf->sys_vars.slice_mask & 0x02) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank10_ic_accesses__read; counter->name = "L3 Bank 10 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 10 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; } if (perf->sys_vars.slice_mask & 0x02) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank10_ic_hits__read; counter->name = "L3 Bank 10 IC Hits"; counter->desc = "The total number of hits in L3 Bank 10 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 308; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; if (perf->sys_vars.slice_mask & 0x02) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank11_accesses__read; counter->name = "L3 Bank 11 Accesses"; counter->desc = "The total number of accesses to L3 Bank 11."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; } if (perf->sys_vars.slice_mask & 0x02) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank13_accesses__read; counter->name = "L3 Bank 13 Accesses"; counter->desc = "The total number of accesses to L3 Bank 13."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 384; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 392; if (perf->sys_vars.slice_mask & 0x02) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank12_accesses__read; counter->name = "L3 Bank 12 Accesses"; counter->desc = "The total number of accesses to L3 Bank 12."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 400; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 408; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 412; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 416; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_data_port_reads_coalescing_mux_regs[114]; static struct gen_perf_query_register_prog bdw_data_port_reads_coalescing_b_counter_regs[24]; static struct gen_perf_query_register_prog bdw_data_port_reads_coalescing_flex_regs[7]; static struct gen_perf_query_counter bdw_data_port_reads_coalescing_query_counters[35]; static struct gen_perf_query_info bdw_data_port_reads_coalescing_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Data Port Reads Coalescing Gen8", .guid = "857fc630-2f09-4804-85f1-084adfadd5ab", .counters = bdw_data_port_reads_coalescing_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_data_port_reads_coalescing_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_data_port_reads_coalescing_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_data_port_reads_coalescing_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_data_port_reads_coalescing_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_data_port_reads_coalescing_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.subslice_mask & 0x01) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103D0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163D240B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1058022F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5520 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063D00B0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D0182 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D10A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D11A2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E582242 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00586700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0658C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C58C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B6300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0639A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B0062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0xBA98BA98 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0xBA98BA98 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00003377 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFF2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FF0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFE2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00007FF0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FFC2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00007FF0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FF82 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x00007FF0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__data_port_reads_coalescing__avg_gpu_core_frequency__max(perf); counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read; counter->name = "EU to Data Port 0 Reads 64"; counter->desc = "The subslice 0 EU data reads from Data Port with 64B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read; counter->name = "Data Port 0 to L3 Data Reads"; counter->desc = "The subslice 0 Data Port data and constant reads from L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_data_writes__read; counter->name = "Data Port 0 to L3 Data Writes"; counter->desc = "The subslice 0 Data Port data writes to L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read; counter->name = "EU to Data Port 0 Reads 128"; counter->desc = "The subslice 0 EU data reads from Data Port with 128B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_writes__read; counter->name = "All Data Port 0 Writes to L3"; counter->desc = "The subslice 0 Data Port writes to L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read; counter->name = "EU to Data Port 0 Reads 32"; counter->desc = "The subslice 0 EU data reads from Data Port with 32B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read; counter->name = "EU to Data Port 0 Reads 256"; counter->desc = "The subslice 0 EU data reads from Data Port with 256B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read; counter->name = "EuBytesReadPerCacheLine"; counter->desc = "Average EU bytes read per L3 cache line."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_data_reads_per_cache_line__read; counter->name = "EuDataReadsPerCacheLine"; counter->desc = "Coalescing ratio of EU read requests to L3 cache lines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_reads__read; counter->name = "All Data Port 0 Reads from L3"; counter->desc = "The subslice 0 Data Port reads from L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_data_port_writes_coalescing_mux_regs[110]; static struct gen_perf_query_register_prog bdw_data_port_writes_coalescing_b_counter_regs[24]; static struct gen_perf_query_register_prog bdw_data_port_writes_coalescing_flex_regs[7]; static struct gen_perf_query_counter bdw_data_port_writes_coalescing_query_counters[38]; static struct gen_perf_query_info bdw_data_port_writes_coalescing_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Data Port Writes Coalescing Gen8", .guid = "343ebc99-4a55-414c-8c17-d8e259cf5e20", .counters = bdw_data_port_writes_coalescing_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_data_port_writes_coalescing_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_data_port_writes_coalescing_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_data_port_writes_coalescing_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_data_port_writes_coalescing_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_data_port_writes_coalescing_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.subslice_mask & 0x01) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103D0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143D0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163D2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1058022F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063D0094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D0182 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D1814 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E582242 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00586700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0658C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B6A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0141 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0282 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381415 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0639A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A82A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B0062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B1555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21852AAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23850028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830141 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0xBA98BA98 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0xBA98BA98 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00003377 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FF72 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FF62 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FF42 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FF02 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0005FFF2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0005FFE2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0005FFC2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BFD0 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0005FF82 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BFD0 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read; counter->name = "EU to Data Port 0 Writes 128"; counter->desc = "The subslice 0 EU data simd16 writes to Data Port with 192B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read; counter->name = "EU to Data Port 0 Writes 32B"; counter->desc = "The subslice 0 EU data writes to Data Port with 32B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__data_port_writes_coalescing__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read; counter->name = "EU to Data Port 0 Writes 256B"; counter->desc = "The subslice 0 EU data simd16 writes to Data Port with 256B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_data_reads__read; counter->name = "Data Port 0 to L3 Data Reads"; counter->desc = "The subslice 0 Data Port data and constant reads from L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read; counter->name = "Data Port 0 to L3 Data Writes"; counter->desc = "The subslice 0 Data Port data writes to L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read; counter->name = "EU to Data Port 0 Writes 64B"; counter->desc = "The subslice 0 EU data simd16 writes to Data Port with 128B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read; counter->name = "EU to Data Port 0 Writes 64B"; counter->desc = "The subslice 0 EU data writes to Data Port with 64B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_writes__read; counter->name = "All Data Port 0 Writes to L3"; counter->desc = "The subslice 0 Data Port writes to L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read; counter->name = "EU to Data Port 0 Writes 64B"; counter->desc = "The subslice 0 EU data writes to Data Port with 64B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read; counter->name = "EU to Data Port 0 Writes 128"; counter->desc = "The subslice 0 EU data writes to Data Port with 128B per message."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read; counter->name = "EuBytesWrittenPerCacheLine"; counter->desc = "Average EU bytes written per L3 cache line."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_data_writes_per_cache_line__read; counter->name = "EuDataWritesPerCacheLine"; counter->desc = "Coalescing ratio of EU write requests to L3 cache lines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 220; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_reads__read; counter->name = "All Data Port 0 Reads from L3"; counter->desc = "The subslice 0 Data Port reads from L3 cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_hdc_and_sf_mux_regs[98]; static struct gen_perf_query_register_prog bdw_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog bdw_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter bdw_hdc_and_sf_query_counters[42]; static struct gen_perf_query_info bdw_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e", .counters = bdw_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D80232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118E4400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C6080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00582080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04386080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0638404B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC25C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD825C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB825C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B80154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAA05 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098E05C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AA0A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF7 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_l3_1_mux_regs[91]; static struct gen_perf_query_register_prog bdw_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog bdw_l3_1_flex_regs[7]; static struct gen_perf_query_counter bdw_l3_1_query_counters[39]; static struct gen_perf_query_info bdw_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b", .counters = bdw_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF03DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12990340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF1187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF1205 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BF0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF042B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BF002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04983400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06990034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10990000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00BA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B91000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__l31_bank1_stalled__read; counter->name = "Slice1 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__l31_bank0_stalled__read; counter->name = "Slice1 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__l31_bank1_active__read; counter->name = "Slice1 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice1 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_1__l31_bank0_active__read; counter->name = "Slice1 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice1 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_l3_2_mux_regs[78]; static struct gen_perf_query_register_prog bdw_l3_2_b_counter_regs[22]; static struct gen_perf_query_register_prog bdw_l3_2_flex_regs[7]; static struct gen_perf_query_counter bdw_l3_2_query_counters[39]; static struct gen_perf_query_info bdw_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "446ae59b-ff2e-41c9-b49e-0184a54bf00a", .counters = bdw_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F03DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3F1187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3F1205 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F042B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06190034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10190000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00BA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B4005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_l3_3_mux_regs[94]; static struct gen_perf_query_register_prog bdw_l3_3_b_counter_regs[22]; static struct gen_perf_query_register_prog bdw_l3_3_flex_regs[7]; static struct gen_perf_query_counter bdw_l3_3_query_counters[39]; static struct gen_perf_query_info bdw_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "84a7956f-1ea4-4d0d-837f-e39a0376e38c", .counters = bdw_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121B0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0274 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129B0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0274 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B3400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0793 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04399000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069B0034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBD4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0981 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A0F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800045 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__l31_bank3_active__read; counter->name = "Slice1 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice1 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__l31_bank3_stalled__read; counter->name = "Slice1 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_l3_4_mux_regs[93]; static struct gen_perf_query_register_prog bdw_l3_4_b_counter_regs[22]; static struct gen_perf_query_register_prog bdw_l3_4_flex_regs[7]; static struct gen_perf_query_counter bdw_l3_4_query_counters[39]; static struct gen_perf_query_info bdw_l3_4_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_4", .guid = "92b493d9-df18-4bed-be06-5cac6f2a6f5f", .counters = bdw_l3_4_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_l3_4_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_l3_4_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_l3_4_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_l3_4_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_l3_4_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A3400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0113 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02592000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069A0034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0984 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9C0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__l3_4__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__l31_bank2_active__read; counter->name = "Slice1 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice1 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__l31_bank2_stalled__read; counter->name = "Slice1 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__l3_4__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__l3_4__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_rasterizer_and_pixel_backend_mux_regs[114]; static struct gen_perf_query_register_prog bdw_rasterizer_and_pixel_backend_b_counter_regs[18]; static struct gen_perf_query_register_prog bdw_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter bdw_rasterizer_and_pixel_backend_query_counters[45]; static struct gen_perf_query_info bdw_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "14345c35-cc46-40d0-bb04-6ed1fbb43679", .counters = bdw_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143B000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043C55C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1E0408 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10390000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12397A1F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BB000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BC5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9E0296 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B97A1F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063B0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02594000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081E02C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0260 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003905E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06390BC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02390018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BB0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BB0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BC05C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D91000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FA806 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0142 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B90617 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB90BE0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B52A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B6A95 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0029 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43801080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00001800 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FCFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000600 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000018 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFC }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer1_input_available__read; counter->name = "Slice1 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice1 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_values1_ready__read; counter->name = "Slice1 Pixel Values Ready"; counter->desc = "The percentage of time in which slice1 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_output1_available__read; counter->name = "Slice1 PS Output Available"; counter->desc = "The percentage of time in which slice1 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer1_output_ready__read; counter->name = "Slice1 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice1 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; } if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_data1_ready__read; counter->name = "Slice1 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_sampler_1_mux_regs[126]; static struct gen_perf_query_register_prog bdw_sampler_1_b_counter_regs[12]; static struct gen_perf_query_register_prog bdw_sampler_1_flex_regs[7]; static struct gen_perf_query_counter bdw_sampler_1_query_counters[41]; static struct gen_perf_query_info bdw_sampler_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler_1", .guid = "f0c6ba37-d3d3-4211-91b5-226730312a54", .counters = bdw_sampler_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_sampler_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_sampler_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_sampler_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_sampler_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_sampler_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18921400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B21400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D21400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14D500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B82500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04918000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04927300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10920000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A946000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C959000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E950098 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B20073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B4C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B59890 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D20073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D30020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED59000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D59800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__sampler10_input_available__read; counter->name = "Slice1 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice1 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__sampler12_output_ready__read; counter->name = "Slice1 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__sampler_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__sampler11_input_available__read; counter->name = "Slice1 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice1 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__sampler12_input_available__read; counter->name = "Slice1 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice1 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__sampler10_output_ready__read; counter->name = "Slice1 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_1__sampler11_output_ready__read; counter->name = "Slice1 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_sampler_2_mux_regs[114]; static struct gen_perf_query_register_prog bdw_sampler_2_b_counter_regs[12]; static struct gen_perf_query_register_prog bdw_sampler_2_flex_regs[7]; static struct gen_perf_query_counter bdw_sampler_2_query_counters[41]; static struct gen_perf_query_info bdw_sampler_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler_2", .guid = "30bf3702-48cf-4bca-b412-7cf50bb2f564", .counters = bdw_sampler_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_sampler_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_sampler_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_sampler_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_sampler_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_sampler_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18121400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18321400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18521400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04127300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1813000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A146000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C159000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150098 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04320073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0434C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02359890 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06520073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18530020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E559000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00559800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__sampler_2__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__sampler_2__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__sampler_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_tdl_1_mux_regs[151]; static struct gen_perf_query_register_prog bdw_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog bdw_tdl_1_flex_regs[7]; static struct gen_perf_query_counter bdw_tdl_1_query_counters[47]; static struct gen_perf_query_info bdw_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "238bec85-df05-44f3-b905-d166712f2451", .counters = bdw_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16154D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16352E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16554D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0458C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0415CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0035C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063500CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0454C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0255CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0254 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B8156A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BAA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A947000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C95C5C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B30040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B30020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B41000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B5C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB5C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D31500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D4E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D5C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD5C3C5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800C42 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFF9 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_thread11_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__non_ps_thread12_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__non_ps_thread10_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_thread12_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__ps_thread10_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; } if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__non_ps_thread11_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_1__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_tdl_2_mux_regs[155]; static struct gen_perf_query_register_prog bdw_tdl_2_b_counter_regs[18]; static struct gen_perf_query_register_prog bdw_tdl_2_flex_regs[7]; static struct gen_perf_query_counter bdw_tdl_2_query_counters[47]; static struct gen_perf_query_info bdw_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "24bf02cd-8693-4583-981c-c4165b33da01", .counters = bdw_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16952E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B54D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D52E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382A55 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08146000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16335040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08349000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A341000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083500C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A35C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1853002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A54E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C55C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E55C1C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0494C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0295CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B41000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B5C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B500CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D46000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D5C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D500CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B555A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800882 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45801082 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478014A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF9F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFFB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFD }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__thread_header11_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__thread_header11_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__thread_header12_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__thread_header10_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 220; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__thread_header12_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__thread_header10_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__tdl_2__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_compute_extra_mux_regs[93]; static struct gen_perf_query_register_prog bdw_compute_extra_b_counter_regs[6]; static struct gen_perf_query_register_prog bdw_compute_extra_flex_regs[7]; static struct gen_perf_query_counter bdw_compute_extra_query_counters[5]; static struct gen_perf_query_info bdw_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen8", .guid = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e", .counters = bdw_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_compute_extra_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_compute_extra_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161503E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163503E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165503E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169503E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B503E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D503E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06141000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0435C300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06544000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04942000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0095C300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B44000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D5C300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B3500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801482 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_vme_pipe_mux_regs[87]; static struct gen_perf_query_register_prog bdw_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog bdw_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter bdw_vme_pipe_query_counters[10]; static struct gen_perf_query_info bdw_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen8", .guid = "e1743ca0-7fc8-410b-a066-de7bbb9280b7", .counters = bdw_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bdw_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bdw_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14100812 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14125800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161200C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14300812 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14325800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163200C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B9400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18380155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00100047 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06101A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10100000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0810C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0811C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08126151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A301AC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10300000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C30C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C31C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C326151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16332A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18330001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23850002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800884 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_gpu_busyness_mux_regs[39]; static struct gen_perf_query_register_prog bdw_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter bdw_gpu_busyness_query_counters[9]; static struct gen_perf_query_info bdw_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "0a9eb7be-feee-4275-a139-6d9cedf0fdb0", .counters = bdw_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void bdw_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AF00100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17830100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A700100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D940040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F00085 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24F00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F858800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04708500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10700000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24700000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__gpu_busyness__vdbox1_busy__read; counter->name = "Vdbox1 Ring Busy"; counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_test_oa_mux_regs[14]; static struct gen_perf_query_register_prog bdw_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter bdw_test_oa_query_counters[12]; static struct gen_perf_query_info bdw_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen8", .guid = "d6de6f55-e526-4f79-a6a6-d7315c09044e", .counters = bdw_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void bdw_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B0066 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21850008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bdw_stc__pma_stall_mux_regs[34]; static struct gen_perf_query_register_prog bdw_stc__pma_stall_b_counter_regs[7]; static struct gen_perf_query_counter bdw_stc__pma_stall_query_counters[11]; static struct gen_perf_query_info bdw_stc__pma_stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "e713f347-953e-4d8c-b02f-6be31df2db2b", .counters = bdw_stc__pma_stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bdw_stc__pma_stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bdw_stc__pma_stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void bdw_register_stc__pma_stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bdw_stc__pma_stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041F4AC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061F03D8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21850AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x008000E1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x001FFFE0 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__stc__pma_stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bdw__stc__pma_stall__avg_gpu_core_frequency__max(perf); counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bdw__stc__pma_stall__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bdw__stc__pma_stall__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_bdw(struct gen_perf *perf) { bdw_register_render_basic_counter_query(perf); bdw_register_compute_basic_counter_query(perf); bdw_register_render_pipe_profile_counter_query(perf); bdw_register_memory_reads_counter_query(perf); bdw_register_memory_writes_counter_query(perf); bdw_register_compute_extended_counter_query(perf); bdw_register_compute_l3_cache_counter_query(perf); bdw_register_data_port_reads_coalescing_counter_query(perf); bdw_register_data_port_writes_coalescing_counter_query(perf); bdw_register_hdc_and_sf_counter_query(perf); bdw_register_l3_1_counter_query(perf); bdw_register_l3_2_counter_query(perf); bdw_register_l3_3_counter_query(perf); bdw_register_l3_4_counter_query(perf); bdw_register_rasterizer_and_pixel_backend_counter_query(perf); bdw_register_sampler_1_counter_query(perf); bdw_register_sampler_2_counter_query(perf); bdw_register_tdl_1_counter_query(perf); bdw_register_tdl_2_counter_query(perf); bdw_register_compute_extra_counter_query(perf); bdw_register_vme_pipe_counter_query(perf); bdw_register_gpu_busyness_counter_query(perf); bdw_register_test_oa_counter_query(perf); bdw_register_stc__pma_stall_counter_query(perf); } static struct gen_perf_query_register_prog chv_render_basic_mux_regs[73]; static struct gen_perf_query_register_prog chv_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog chv_render_basic_flex_regs[7]; static struct gen_perf_query_counter chv_render_basic_query_counters[50]; static struct gen_perf_query_info chv_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen8LP", .guid = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb", .counters = chv_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x285A0006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2C110014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2C310014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E310000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B8303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580024F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00580888 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E5A0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x205A0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00190555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021F0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00380444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02390500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0666 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00100111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A110031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E110046 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00130111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00300444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08310030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C310031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10310046 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04310000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00310000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00330444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018B0FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01855000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13830021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1783002F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1983002E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B83002D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D83002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01840555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03840500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23800074 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2580007D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01805000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03800055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01865000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03860055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01875000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03870055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4380000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4780000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 352; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_compute_basic_mux_regs[43]; static struct gen_perf_query_register_prog chv_compute_basic_b_counter_regs[4]; static struct gen_perf_query_register_prog chv_compute_basic_flex_regs[7]; static struct gen_perf_query_counter chv_compute_basic_query_counters[42]; static struct gen_perf_query_info chv_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen8LP", .guid = "f522a89c-ecd1-4522-8331-3383c54af5f5", .counters = chv_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E5800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E3800E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580024F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08580042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C580040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1058004C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1458004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04580000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00580000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00195555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06380042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38004C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1238004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A5555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018BFFFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01845555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17800074 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980007D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80007C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8000B6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F8000B7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x438000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4980012A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B80012A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D80012A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F80012A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x518001CE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x538001CE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5580000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__gti_ring_throughput__read; counter->name = "GTI Ring Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and Uncore ring."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__gti_ro_stall__read; counter->name = "GTI Read-Only Stall"; counter->desc = "The percentage of time in which GTI Read-Only port has been stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__gti_rw_stall__read; counter->name = "GTI Read-Write Stall"; counter->desc = "The percentage of time in which GTI Read-Write port has been stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_render_pipe_profile_mux_regs[82]; static struct gen_perf_query_register_prog chv_render_pipe_profile_b_counter_regs[20]; static struct gen_perf_query_register_prog chv_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter chv_render_pipe_profile_query_counters[44]; static struct gen_perf_query_info chv_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile", .guid = "a9ccc03d-a943-4e6b-9cd6-13e063075927", .counters = chv_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x261E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x281F000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2817001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2791001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27880019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D890000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278A0007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x298D001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278E0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B8F0012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00184000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02181000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x221F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0213C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02164000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24170012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07910005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05910000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01911500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03910501 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D880003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B890032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B890031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05890000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01890040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03890040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A2050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018B95A9 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038BE5A9 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C0501 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178D0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138E0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x218E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018E0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038E0101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8F0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01900100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01845555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03845555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x438000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x458000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478000AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4980018C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B80014B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800128 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F80012A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5380014B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55800149 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5780010A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_hdc_and_sf_mux_regs[98]; static struct gen_perf_query_register_prog chv_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog chv_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter chv_hdc_and_sf_query_counters[42]; static struct gen_perf_query_info chv_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", .counters = chv_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D80232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118E4400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C6080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00582080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04386080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0638404B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC25C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD825C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB825C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B80154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAA05 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098E05C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AA0A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF7 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_l3_1_mux_regs[91]; static struct gen_perf_query_register_prog chv_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog chv_l3_1_flex_regs[7]; static struct gen_perf_query_counter chv_l3_1_query_counters[39]; static struct gen_perf_query_info chv_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "78a87ff9-543a-49ce-95ea-26d86071ea93", .counters = chv_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF03DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12990340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF1187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF1205 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BF0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF042B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BF002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04983400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06990034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10990000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00BA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B91000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__l31_bank1_stalled__read; counter->name = "Slice1 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__l31_bank0_stalled__read; counter->name = "Slice1 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__l31_bank1_active__read; counter->name = "Slice1 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice1 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_1__l31_bank0_active__read; counter->name = "Slice1 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice1 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_l3_2_mux_regs[78]; static struct gen_perf_query_register_prog chv_l3_2_b_counter_regs[22]; static struct gen_perf_query_register_prog chv_l3_2_flex_regs[7]; static struct gen_perf_query_counter chv_l3_2_query_counters[39]; static struct gen_perf_query_info chv_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", .counters = chv_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F03DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3F1187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3F1205 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F042B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F002C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06190034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10190000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00BA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B4005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_l3_3_mux_regs[94]; static struct gen_perf_query_register_prog chv_l3_3_b_counter_regs[22]; static struct gen_perf_query_register_prog chv_l3_3_flex_regs[7]; static struct gen_perf_query_counter chv_l3_3_query_counters[39]; static struct gen_perf_query_info chv_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", .counters = chv_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121B0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0274 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129B0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0274 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B3400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0793 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04399000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069B0034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBD4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0981 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A0F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800045 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__l31_bank3_active__read; counter->name = "Slice1 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice1 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__l31_bank3_stalled__read; counter->name = "Slice1 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_l3_4_mux_regs[93]; static struct gen_perf_query_register_prog chv_l3_4_b_counter_regs[22]; static struct gen_perf_query_register_prog chv_l3_4_flex_regs[7]; static struct gen_perf_query_counter chv_l3_4_query_counters[39]; static struct gen_perf_query_info chv_l3_4_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_4", .guid = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", .counters = chv_l3_4_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_l3_4_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_l3_4_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_l3_4_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_l3_4_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_l3_4_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A3400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0113 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02592000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069A0034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0984 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9C0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__l3_4__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__l31_bank2_active__read; counter->name = "Slice1 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice1 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__l31_bank2_stalled__read; counter->name = "Slice1 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__l3_4__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__l3_4__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_rasterizer_and_pixel_backend_mux_regs[114]; static struct gen_perf_query_register_prog chv_rasterizer_and_pixel_backend_b_counter_regs[18]; static struct gen_perf_query_register_prog chv_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter chv_rasterizer_and_pixel_backend_query_counters[45]; static struct gen_perf_query_info chv_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", .counters = chv_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143B000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043C55C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1E0408 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10390000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12397A1F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BB000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BC5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9E0296 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B97A1F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063B0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02594000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081E02C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0260 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003905E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06390BC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02390018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BB0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BB0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BC05C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D91000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FA806 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0142 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B90617 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB90BE0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B52A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B6A95 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0029 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43801080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00001800 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FCFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000600 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000018 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFC }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer1_input_available__read; counter->name = "Slice1 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice1 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied))"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_values1_ready__read; counter->name = "Slice1 Pixel Values Ready"; counter->desc = "The percentage of time in which slice1 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_output1_available__read; counter->name = "Slice1 PS Output Available"; counter->desc = "The percentage of time in which slice1 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer1_output_ready__read; counter->name = "Slice1 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice1 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; } if (perf->sys_vars.slice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_data1_ready__read; counter->name = "Slice1 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_sampler_1_mux_regs[126]; static struct gen_perf_query_register_prog chv_sampler_1_b_counter_regs[12]; static struct gen_perf_query_register_prog chv_sampler_1_flex_regs[7]; static struct gen_perf_query_counter chv_sampler_1_query_counters[41]; static struct gen_perf_query_info chv_sampler_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler_1", .guid = "71148d78-baf5-474f-878a-e23158d0265d", .counters = chv_sampler_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_sampler_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_sampler_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_sampler_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_sampler_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_sampler_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18921400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B21400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D21400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14D500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B82500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04918000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04927300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10920000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A946000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C959000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E950098 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B20073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B4C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B59890 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D20073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D30020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED59000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D59800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__sampler10_input_available__read; counter->name = "Slice1 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice1 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__sampler12_output_ready__read; counter->name = "Slice1 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__sampler_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__sampler11_input_available__read; counter->name = "Slice1 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice1 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__sampler12_input_available__read; counter->name = "Slice1 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice1 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__sampler10_output_ready__read; counter->name = "Slice1 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_1__sampler11_output_ready__read; counter->name = "Slice1 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_sampler_2_mux_regs[114]; static struct gen_perf_query_register_prog chv_sampler_2_b_counter_regs[12]; static struct gen_perf_query_register_prog chv_sampler_2_flex_regs[7]; static struct gen_perf_query_counter chv_sampler_2_query_counters[41]; static struct gen_perf_query_info chv_sampler_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler_2", .guid = "b996a2b7-c59c-492d-877a-8cd54fd6df84", .counters = chv_sampler_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_sampler_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_sampler_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_sampler_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_sampler_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_sampler_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18121400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18321400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18521400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145500AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04127300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1813000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A146000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C159000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150098 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04320073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0434C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02359890 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06520073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18530020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E559000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00559800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__sampler_2__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__sampler_2__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__sampler_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_tdl_1_mux_regs[151]; static struct gen_perf_query_register_prog chv_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog chv_tdl_1_flex_regs[7]; static struct gen_perf_query_counter chv_tdl_1_query_counters[47]; static struct gen_perf_query_info chv_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "eb2fecba-b431-42e7-8261-fe9429a6e67a", .counters = chv_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16154D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16352E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16554D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0458C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06388000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0415CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C338000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0035C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063500CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0454C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0255CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0254 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B8156A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BAA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A947000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C95C5C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B30040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B30020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B41000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B5C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB5C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D31500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D4E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D5C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD5C3C5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800C42 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFF9 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_thread11_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__non_ps_thread12_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__non_ps_thread10_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_thread12_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__ps_thread10_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; } if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__non_ps_thread11_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_1__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_tdl_2_mux_regs[155]; static struct gen_perf_query_register_prog chv_tdl_2_b_counter_regs[18]; static struct gen_perf_query_register_prog chv_tdl_2_flex_regs[7]; static struct gen_perf_query_counter chv_tdl_2_query_counters[47]; static struct gen_perf_query_info chv_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "60749470-a648-4a4b-9f10-dbfe1e36e44d", .counters = chv_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = chv_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void chv_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16952E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B54D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D52E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08588000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A584000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382A55 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08146000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16335040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08349000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A341000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083500C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A35C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3500C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1853002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A54E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C55C500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E55C1C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BD8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D8C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0494C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0295CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B41000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B5C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B500CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D46000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D5C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D500CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B555A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800882 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45801082 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478014A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF9F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFFB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFD }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__thread_header11_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; if (perf->sys_vars.subslice_mask & 0x10) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__thread_header11_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__thread_header12_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__thread_header10_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 220; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } if (perf->sys_vars.subslice_mask & 0x20) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__thread_header12_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; if (perf->sys_vars.subslice_mask & 0x8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__thread_header10_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = chv__tdl_2__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog chv_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog chv_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter chv_test_oa_query_counters[12]; static struct gen_perf_query_info chv_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen8LP", .guid = "4a534b07-cba3-414d-8d60-874830e883aa", .counters = chv_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = chv_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = chv_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void chv_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &chv_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x338B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0066 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x001823A4, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = chv__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = chv__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_chv(struct gen_perf *perf) { chv_register_render_basic_counter_query(perf); chv_register_compute_basic_counter_query(perf); chv_register_render_pipe_profile_counter_query(perf); chv_register_hdc_and_sf_counter_query(perf); chv_register_l3_1_counter_query(perf); chv_register_l3_2_counter_query(perf); chv_register_l3_3_counter_query(perf); chv_register_l3_4_counter_query(perf); chv_register_rasterizer_and_pixel_backend_counter_query(perf); chv_register_sampler_1_counter_query(perf); chv_register_sampler_2_counter_query(perf); chv_register_tdl_1_counter_query(perf); chv_register_tdl_2_counter_query(perf); chv_register_test_oa_counter_query(perf); } static struct gen_perf_query_register_prog sklgt2_render_basic_mux_regs[70]; static struct gen_perf_query_register_prog sklgt2_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog sklgt2_render_basic_flex_regs[7]; static struct gen_perf_query_counter sklgt2_render_basic_query_counters[52]; static struct gen_perf_query_info sklgt2_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "07b25942-d9fd-4fce-bd58-e29abd66b7de", .counters = sklgt2_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.revision >= 0x02) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C2200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51904400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_compute_basic_mux_regs[155]; static struct gen_perf_query_register_prog sklgt2_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog sklgt2_compute_basic_flex_regs[7]; static struct gen_perf_query_counter sklgt2_compute_basic_query_counters[39]; static struct gen_perf_query_info sklgt2_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "00b80b4c-d215-4378-9015-da3dda3b61ea", .counters = sklgt2_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if ((perf->sys_vars.slice_mask & 0x01) && (perf->sys_vars.revision < 0x02)) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901403 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0DB2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E3C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F1D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C002D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0082 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CBE00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00EF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if ((perf->sys_vars.slice_mask & 0x01) && (perf->sys_vars.revision >= 0x02)) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901403 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1810 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_render_pipe_profile_mux_regs[230]; static struct gen_perf_query_register_prog sklgt2_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog sklgt2_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter sklgt2_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info sklgt2_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "2a0c0933-37e7-427c-9951-ded42a78bb27", .counters = sklgt2_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.revision < 0x02) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F96C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F950011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F974000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11974000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09974000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419010A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x499000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900081 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.revision >= 0x02) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419010A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x499000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900081 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_memory_reads_mux_regs[167]; static struct gen_perf_query_register_prog sklgt2_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog sklgt2_memory_reads_flex_regs[7]; static struct gen_perf_query_counter sklgt2_memory_reads_query_counters[41]; static struct gen_perf_query_info sklgt2_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "246b35f1-44e0-4d03-8936-e452e291d064", .counters = sklgt2_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if ((perf->sys_vars.slice_mask & 0x01) && (perf->sys_vars.revision < 0x02)) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13946000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1196C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93FE00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B954000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D95A550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F9502AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if ((perf->sys_vars.revision < 0x05) && (perf->sys_vars.revision >= 0x02)) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13946000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15940016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93AA55 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D9300AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F940018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E57000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C20 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } if (perf->sys_vars.revision >= 0x05) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_memory_writes_mux_regs[213]; static struct gen_perf_query_register_prog sklgt2_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog sklgt2_memory_writes_flex_regs[7]; static struct gen_perf_query_counter sklgt2_memory_writes_query_counters[41]; static struct gen_perf_query_info sklgt2_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "e0d3da02-00bf-4a96-9795-b48158c73a68", .counters = sklgt2_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if ((perf->sys_vars.slice_mask & 0x01) && (perf->sys_vars.revision < 0x02)) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13945400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1196C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93FE00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B954000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D95A550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F9502AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; } if ((perf->sys_vars.revision < 0x05) && (perf->sys_vars.revision >= 0x02)) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13945400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93AA55 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D93002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E57000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C20 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_compute_extended_mux_regs[73]; static struct gen_perf_query_register_prog sklgt2_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog sklgt2_compute_extended_flex_regs[7]; static struct gen_perf_query_counter sklgt2_compute_extended_query_counters[38]; static struct gen_perf_query_info sklgt2_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "c26b1fda-2752-4a33-a448-4c8718366846", .counters = sklgt2_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.subslice_mask & 0x01) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_compute_l3_cache_mux_regs[61]; static struct gen_perf_query_register_prog sklgt2_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog sklgt2_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter sklgt2_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info sklgt2_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "9fb22842-e708-43f7-9752-e0e41670c39e", .counters = sklgt2_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901403 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_hdc_and_sf_mux_regs[55]; static struct gen_perf_query_register_prog sklgt2_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog sklgt2_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter sklgt2_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info sklgt2_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "5378e2a1-4248-4188-a4ae-da25a794c603", .counters = sklgt2_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_l3_1_mux_regs[72]; static struct gen_perf_query_register_prog sklgt2_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog sklgt2_l3_1_flex_regs[7]; static struct gen_perf_query_counter sklgt2_l3_1_query_counters[39]; static struct gen_perf_query_info sklgt2_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "f42cdd6a-b000-42cb-870f-5eb423a7f514", .counters = sklgt2_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_l3_2_mux_regs[45]; static struct gen_perf_query_register_prog sklgt2_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog sklgt2_l3_2_flex_regs[7]; static struct gen_perf_query_counter sklgt2_l3_2_query_counters[37]; static struct gen_perf_query_info sklgt2_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "b9bf2423-d88c-4a7b-a051-627611d00dcc", .counters = sklgt2_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_l3_3_mux_regs[44]; static struct gen_perf_query_register_prog sklgt2_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog sklgt2_l3_3_flex_regs[7]; static struct gen_perf_query_counter sklgt2_l3_3_query_counters[37]; static struct gen_perf_query_info sklgt2_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "2414a93d-d84f-406e-99c0-472161194b40", .counters = sklgt2_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_rasterizer_and_pixel_backend_mux_regs[32]; static struct gen_perf_query_register_prog sklgt2_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog sklgt2_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter sklgt2_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info sklgt2_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5", .counters = sklgt2_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_sampler_mux_regs[70]; static struct gen_perf_query_register_prog sklgt2_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog sklgt2_sampler_flex_regs[7]; static struct gen_perf_query_counter sklgt2_sampler_query_counters[41]; static struct gen_perf_query_info sklgt2_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "b4cff514-a91e-4798-a0b3-426ca13fc9c1", .counters = sklgt2_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_tdl_1_mux_regs[69]; static struct gen_perf_query_register_prog sklgt2_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog sklgt2_tdl_1_flex_regs[7]; static struct gen_perf_query_counter sklgt2_tdl_1_query_counters[41]; static struct gen_perf_query_info sklgt2_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "7821d13b-9b8b-4405-9618-78cd56b62cce", .counters = sklgt2_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_tdl_2_mux_regs[43]; static struct gen_perf_query_register_prog sklgt2_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog sklgt2_tdl_2_flex_regs[7]; static struct gen_perf_query_counter sklgt2_tdl_2_query_counters[41]; static struct gen_perf_query_info sklgt2_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "893f1a4d-919d-4388-8cb7-746d73ea7259", .counters = sklgt2_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_compute_extra_mux_regs[32]; static struct gen_perf_query_register_prog sklgt2_compute_extra_b_counter_regs[6]; static struct gen_perf_query_register_prog sklgt2_compute_extra_flex_regs[7]; static struct gen_perf_query_counter sklgt2_compute_extra_query_counters[5]; static struct gen_perf_query_info sklgt2_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "41a24047-7484-4ead-ae37-de907e5ff2b2", .counters = sklgt2_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_compute_extra_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_compute_extra_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_vme_pipe_mux_regs[62]; static struct gen_perf_query_register_prog sklgt2_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog sklgt2_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter sklgt2_vme_pipe_query_counters[10]; static struct gen_perf_query_info sklgt2_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "95910492-943f-44bd-9461-390240f243fd", .counters = sklgt2_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt2_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14380002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06393000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A33F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C33F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A37A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C37A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06383000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900844 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_gpu_busyness_mux_regs[34]; static struct gen_perf_query_register_prog sklgt2_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter sklgt2_gpu_busyness_query_counters[8]; static struct gen_perf_query_info sklgt2_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "c44a5cf7-886d-477b-bebd-2d738923e4c3", .counters = sklgt2_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog sklgt2_test_oa_b_counter_regs[21]; static struct gen_perf_query_counter sklgt2_test_oa_query_counters[12]; static struct gen_perf_query_info sklgt2_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "1651949f-0ac0-4cb1-a06f-dafd74a407d1", .counters = sklgt2_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt2_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog sklgt2_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter sklgt2_pma__stall_query_counters[4]; static struct gen_perf_query_info sklgt2_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "27871149-2fa9-40ba-aa73-350d60c03a09", .counters = sklgt2_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt2_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt2_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt2_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt2_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt2__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt2__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt2__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_sklgt2(struct gen_perf *perf) { sklgt2_register_render_basic_counter_query(perf); sklgt2_register_compute_basic_counter_query(perf); sklgt2_register_render_pipe_profile_counter_query(perf); sklgt2_register_memory_reads_counter_query(perf); sklgt2_register_memory_writes_counter_query(perf); sklgt2_register_compute_extended_counter_query(perf); sklgt2_register_compute_l3_cache_counter_query(perf); sklgt2_register_hdc_and_sf_counter_query(perf); sklgt2_register_l3_1_counter_query(perf); sklgt2_register_l3_2_counter_query(perf); sklgt2_register_l3_3_counter_query(perf); sklgt2_register_rasterizer_and_pixel_backend_counter_query(perf); sklgt2_register_sampler_counter_query(perf); sklgt2_register_tdl_1_counter_query(perf); sklgt2_register_tdl_2_counter_query(perf); sklgt2_register_compute_extra_counter_query(perf); sklgt2_register_vme_pipe_counter_query(perf); sklgt2_register_gpu_busyness_counter_query(perf); sklgt2_register_test_oa_counter_query(perf); sklgt2_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog sklgt3_render_basic_mux_regs[83]; static struct gen_perf_query_register_prog sklgt3_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog sklgt3_render_basic_flex_regs[7]; static struct gen_perf_query_counter sklgt3_render_basic_query_counters[52]; static struct gen_perf_query_info sklgt3_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "21fef15a-83f4-4ffa-bb81-7da6e38b8e4b", .counters = sklgt3_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CA200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51907710 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419020A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55901515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900529 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57907770 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49902100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900108 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43902108 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53907777 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_compute_basic_mux_regs[78]; static struct gen_perf_query_register_prog sklgt3_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog sklgt3_compute_basic_flex_regs[7]; static struct gen_perf_query_counter sklgt3_compute_basic_query_counters[39]; static struct gen_perf_query_info sklgt3_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "4320492b-fd03-42ac-922f-dbe1ef3b7b58", .counters = sklgt3_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900863 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C62 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53903333 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_render_pipe_profile_mux_regs[114]; static struct gen_perf_query_register_prog sklgt3_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog sklgt3_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter sklgt3_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info sklgt3_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d", .counters = sklgt3_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51901150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55905111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x479004A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57903455 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900455 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_memory_reads_mux_regs[47]; static struct gen_perf_query_register_prog sklgt3_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog sklgt3_memory_reads_flex_regs[7]; static struct gen_perf_query_counter sklgt3_memory_reads_query_counters[41]; static struct gen_perf_query_info sklgt3_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "4ca0f3fe-7fd3-4924-98cb-1807d9879767", .counters = sklgt3_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_memory_writes_mux_regs[47]; static struct gen_perf_query_register_prog sklgt3_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog sklgt3_memory_writes_flex_regs[7]; static struct gen_perf_query_counter sklgt3_memory_writes_query_counters[41]; static struct gen_perf_query_info sklgt3_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "a0c0172c-ee13-403d-99ff-2bdf6936cf14", .counters = sklgt3_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_compute_extended_mux_regs[72]; static struct gen_perf_query_register_prog sklgt3_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog sklgt3_compute_extended_flex_regs[7]; static struct gen_perf_query_counter sklgt3_compute_extended_query_counters[38]; static struct gen_perf_query_info sklgt3_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "52435e0b-f188-42ea-8680-21a56ee20dee", .counters = sklgt3_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_compute_l3_cache_mux_regs[60]; static struct gen_perf_query_register_prog sklgt3_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog sklgt3_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter sklgt3_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info sklgt3_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "27076eeb-49f3-4fed-8423-c66506005c63", .counters = sklgt3_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53903333 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900840 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_hdc_and_sf_mux_regs[54]; static struct gen_perf_query_register_prog sklgt3_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog sklgt3_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter sklgt3_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info sklgt3_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "8071b409-c39a-4674-94d7-32962ecfb512", .counters = sklgt3_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_l3_1_mux_regs[71]; static struct gen_perf_query_register_prog sklgt3_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog sklgt3_l3_1_flex_regs[7]; static struct gen_perf_query_counter sklgt3_l3_1_query_counters[39]; static struct gen_perf_query_info sklgt3_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed", .counters = sklgt3_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_l3_2_mux_regs[44]; static struct gen_perf_query_register_prog sklgt3_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog sklgt3_l3_2_flex_regs[7]; static struct gen_perf_query_counter sklgt3_l3_2_query_counters[37]; static struct gen_perf_query_info sklgt3_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "25dc828e-1d2d-426e-9546-a1d4233cdf16", .counters = sklgt3_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_l3_3_mux_regs[43]; static struct gen_perf_query_register_prog sklgt3_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog sklgt3_l3_3_flex_regs[7]; static struct gen_perf_query_counter sklgt3_l3_3_query_counters[37]; static struct gen_perf_query_info sklgt3_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "3dba9405-2d7e-4d70-8199-e734e82fd6bf", .counters = sklgt3_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_rasterizer_and_pixel_backend_mux_regs[31]; static struct gen_perf_query_register_prog sklgt3_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog sklgt3_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter sklgt3_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info sklgt3_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5", .counters = sklgt3_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_sampler_mux_regs[69]; static struct gen_perf_query_register_prog sklgt3_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog sklgt3_sampler_flex_regs[7]; static struct gen_perf_query_counter sklgt3_sampler_query_counters[41]; static struct gen_perf_query_info sklgt3_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6", .counters = sklgt3_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_tdl_1_mux_regs[68]; static struct gen_perf_query_register_prog sklgt3_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog sklgt3_tdl_1_flex_regs[7]; static struct gen_perf_query_counter sklgt3_tdl_1_query_counters[41]; static struct gen_perf_query_info sklgt3_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "b375c985-9953-455b-bda2-b03f7594e9db", .counters = sklgt3_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_tdl_2_mux_regs[42]; static struct gen_perf_query_register_prog sklgt3_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog sklgt3_tdl_2_flex_regs[7]; static struct gen_perf_query_counter sklgt3_tdl_2_query_counters[41]; static struct gen_perf_query_info sklgt3_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d", .counters = sklgt3_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_compute_extra_mux_regs[69]; static struct gen_perf_query_counter sklgt3_compute_extra_query_counters[5]; static struct gen_perf_query_info sklgt3_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221", .counters = sklgt3_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900402 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_vme_pipe_mux_regs[73]; static struct gen_perf_query_register_prog sklgt3_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog sklgt3_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter sklgt3_vme_pipe_query_counters[10]; static struct gen_perf_query_info sklgt3_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "cfae9232-6ffc-42cc-a703-9790016925f0", .counters = sklgt3_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt3_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900115 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900884 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_gpu_busyness_mux_regs[43]; static struct gen_perf_query_register_prog sklgt3_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter sklgt3_gpu_busyness_query_counters[9]; static struct gen_perf_query_info sklgt3_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "0c5058ff-fdf4-4e0d-81fb-c0310fb76525", .counters = sklgt3_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21D05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11D00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__gpu_busyness__vdbox1_busy__read; counter->name = "Vdbox1 Ring Busy"; counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog sklgt3_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter sklgt3_test_oa_query_counters[12]; static struct gen_perf_query_info sklgt3_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "2b985803-d3c9-4629-8a4f-634bfecba0e8", .counters = sklgt3_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt3_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog sklgt3_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter sklgt3_pma__stall_query_counters[4]; static struct gen_perf_query_info sklgt3_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "c889fd93-8dc7-4ba5-9451-de34a8b5ea3f", .counters = sklgt3_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt3_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt3_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt3_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt3_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt3__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt3__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt3__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_sklgt3(struct gen_perf *perf) { sklgt3_register_render_basic_counter_query(perf); sklgt3_register_compute_basic_counter_query(perf); sklgt3_register_render_pipe_profile_counter_query(perf); sklgt3_register_memory_reads_counter_query(perf); sklgt3_register_memory_writes_counter_query(perf); sklgt3_register_compute_extended_counter_query(perf); sklgt3_register_compute_l3_cache_counter_query(perf); sklgt3_register_hdc_and_sf_counter_query(perf); sklgt3_register_l3_1_counter_query(perf); sklgt3_register_l3_2_counter_query(perf); sklgt3_register_l3_3_counter_query(perf); sklgt3_register_rasterizer_and_pixel_backend_counter_query(perf); sklgt3_register_sampler_counter_query(perf); sklgt3_register_tdl_1_counter_query(perf); sklgt3_register_tdl_2_counter_query(perf); sklgt3_register_compute_extra_counter_query(perf); sklgt3_register_vme_pipe_counter_query(perf); sklgt3_register_gpu_busyness_counter_query(perf); sklgt3_register_test_oa_counter_query(perf); sklgt3_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog sklgt4_render_basic_mux_regs[94]; static struct gen_perf_query_register_prog sklgt4_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog sklgt4_render_basic_flex_regs[7]; static struct gen_perf_query_counter sklgt4_render_basic_query_counters[51]; static struct gen_perf_query_info sklgt4_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "95322a71-bb05-4437-bc27-f7dd7b27d136", .counters = sklgt4_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x176C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E03B0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CA400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0230 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x088D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B4E0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x096C5300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x116C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x091B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x090D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x172C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5190FF30 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55903033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900803 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5790FFF1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5990000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5390FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_compute_basic_mux_regs[78]; static struct gen_perf_query_register_prog sklgt4_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog sklgt4_compute_basic_flex_regs[7]; static struct gen_perf_query_counter sklgt4_compute_basic_query_counters[39]; static struct gen_perf_query_info sklgt4_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "7277228f-e7f3-4743-945a-6a2049d11377", .counters = sklgt4_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53905555 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_render_pipe_profile_mux_regs[114]; static struct gen_perf_query_register_prog sklgt4_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog sklgt4_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter sklgt4_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info sklgt4_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "463c668c-3f60-49b6-8f85-d995b635b3b2", .counters = sklgt4_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51901110 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55901111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57901411 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900411 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_memory_reads_mux_regs[47]; static struct gen_perf_query_register_prog sklgt4_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog sklgt4_memory_reads_flex_regs[7]; static struct gen_perf_query_counter sklgt4_memory_reads_query_counters[41]; static struct gen_perf_query_info sklgt4_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8", .counters = sklgt4_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_memory_writes_mux_regs[47]; static struct gen_perf_query_register_prog sklgt4_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog sklgt4_memory_writes_flex_regs[7]; static struct gen_perf_query_counter sklgt4_memory_writes_query_counters[41]; static struct gen_perf_query_info sklgt4_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "055f256d-4052-467c-8dec-6064a4806433", .counters = sklgt4_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_compute_extended_mux_regs[72]; static struct gen_perf_query_register_prog sklgt4_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog sklgt4_compute_extended_flex_regs[7]; static struct gen_perf_query_counter sklgt4_compute_extended_query_counters[38]; static struct gen_perf_query_info sklgt4_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "753972d4-87cd-4460-824d-754463ac5054", .counters = sklgt4_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_compute_l3_cache_mux_regs[60]; static struct gen_perf_query_register_prog sklgt4_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog sklgt4_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter sklgt4_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info sklgt4_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "4e4392e9-8f73-457b-ab44-b49f7a0c733b", .counters = sklgt4_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53905555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_hdc_and_sf_mux_regs[54]; static struct gen_perf_query_register_prog sklgt4_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog sklgt4_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter sklgt4_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info sklgt4_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805", .counters = sklgt4_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_l3_1_mux_regs[71]; static struct gen_perf_query_register_prog sklgt4_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog sklgt4_l3_1_flex_regs[7]; static struct gen_perf_query_counter sklgt4_l3_1_query_counters[39]; static struct gen_perf_query_info sklgt4_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "d9e86d70-462b-462a-851e-fd63e8c13d63", .counters = sklgt4_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_l3_2_mux_regs[44]; static struct gen_perf_query_register_prog sklgt4_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog sklgt4_l3_2_flex_regs[7]; static struct gen_perf_query_counter sklgt4_l3_2_query_counters[37]; static struct gen_perf_query_info sklgt4_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "52200424-6ee9-48b3-b7fa-0afcf1975e4d", .counters = sklgt4_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_l3_3_mux_regs[43]; static struct gen_perf_query_register_prog sklgt4_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog sklgt4_l3_3_flex_regs[7]; static struct gen_perf_query_counter sklgt4_l3_3_query_counters[37]; static struct gen_perf_query_info sklgt4_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "1988315f-0a26-44df-acb0-df7ec86b1456", .counters = sklgt4_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_rasterizer_and_pixel_backend_mux_regs[31]; static struct gen_perf_query_register_prog sklgt4_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog sklgt4_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter sklgt4_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info sklgt4_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d", .counters = sklgt4_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_sampler_mux_regs[69]; static struct gen_perf_query_register_prog sklgt4_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog sklgt4_sampler_flex_regs[7]; static struct gen_perf_query_counter sklgt4_sampler_query_counters[41]; static struct gen_perf_query_info sklgt4_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b", .counters = sklgt4_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_tdl_1_mux_regs[68]; static struct gen_perf_query_register_prog sklgt4_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog sklgt4_tdl_1_flex_regs[7]; static struct gen_perf_query_counter sklgt4_tdl_1_query_counters[41]; static struct gen_perf_query_info sklgt4_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3", .counters = sklgt4_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_tdl_2_mux_regs[42]; static struct gen_perf_query_register_prog sklgt4_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog sklgt4_tdl_2_flex_regs[7]; static struct gen_perf_query_counter sklgt4_tdl_2_query_counters[41]; static struct gen_perf_query_info sklgt4_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "97875e21-6624-4aee-9191-682feb3eae21", .counters = sklgt4_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_compute_extra_mux_regs[112]; static struct gen_perf_query_counter sklgt4_compute_extra_query_counters[4]; static struct gen_perf_query_info sklgt4_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd", .counters = sklgt4_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x131203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x133203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x135203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACEF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CCE0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC02A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x072F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D4C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x110F01B0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x192C0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F121980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D521980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51901100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901423 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53903331 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900044 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_vme_pipe_mux_regs[73]; static struct gen_perf_query_register_prog sklgt4_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog sklgt4_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter sklgt4_vme_pipe_query_counters[10]; static struct gen_perf_query_info sklgt4_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e", .counters = sklgt4_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = sklgt4_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900821 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_gpu_busyness_mux_regs[43]; static struct gen_perf_query_register_prog sklgt4_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter sklgt4_gpu_busyness_query_counters[9]; static struct gen_perf_query_info sklgt4_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "4e5b1599-5b01-4b3d-89fa-6b26a25fe02b", .counters = sklgt4_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21D05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11D00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__gpu_busyness__vdbox1_busy__read; counter->name = "Vdbox1 Ring Busy"; counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog sklgt4_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter sklgt4_test_oa_query_counters[12]; static struct gen_perf_query_info sklgt4_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "882fa433-1f4a-4a67-a962-c741888fe5f5", .counters = sklgt4_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog sklgt4_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog sklgt4_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter sklgt4_pma__stall_query_counters[4]; static struct gen_perf_query_info sklgt4_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "befe9fd6-474e-4a3d-b98e-cd793715cf91", .counters = sklgt4_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = sklgt4_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = sklgt4_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void sklgt4_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &sklgt4_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = sklgt4__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = sklgt4__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = sklgt4__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_sklgt4(struct gen_perf *perf) { sklgt4_register_render_basic_counter_query(perf); sklgt4_register_compute_basic_counter_query(perf); sklgt4_register_render_pipe_profile_counter_query(perf); sklgt4_register_memory_reads_counter_query(perf); sklgt4_register_memory_writes_counter_query(perf); sklgt4_register_compute_extended_counter_query(perf); sklgt4_register_compute_l3_cache_counter_query(perf); sklgt4_register_hdc_and_sf_counter_query(perf); sklgt4_register_l3_1_counter_query(perf); sklgt4_register_l3_2_counter_query(perf); sklgt4_register_l3_3_counter_query(perf); sklgt4_register_rasterizer_and_pixel_backend_counter_query(perf); sklgt4_register_sampler_counter_query(perf); sklgt4_register_tdl_1_counter_query(perf); sklgt4_register_tdl_2_counter_query(perf); sklgt4_register_compute_extra_counter_query(perf); sklgt4_register_vme_pipe_counter_query(perf); sklgt4_register_gpu_busyness_counter_query(perf); sklgt4_register_test_oa_counter_query(perf); sklgt4_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog kblgt2_render_basic_mux_regs[70]; static struct gen_perf_query_register_prog kblgt2_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog kblgt2_render_basic_flex_regs[7]; static struct gen_perf_query_counter kblgt2_render_basic_query_counters[52]; static struct gen_perf_query_info kblgt2_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "99c1a40e-a090-4354-86e3-4d068bb1917e", .counters = kblgt2_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C2200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51904400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_compute_basic_mux_regs[78]; static struct gen_perf_query_register_prog kblgt2_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog kblgt2_compute_basic_flex_regs[7]; static struct gen_perf_query_counter kblgt2_compute_basic_query_counters[39]; static struct gen_perf_query_info kblgt2_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "e17fc42a-e614-41b6-90c4-1074841a6c77", .counters = kblgt2_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_render_pipe_profile_mux_regs[114]; static struct gen_perf_query_register_prog kblgt2_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog kblgt2_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter kblgt2_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info kblgt2_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "d7a17a3a-ca71-40d2-a919-ace80d50633f", .counters = kblgt2_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_memory_reads_mux_regs[47]; static struct gen_perf_query_register_prog kblgt2_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog kblgt2_memory_reads_flex_regs[7]; static struct gen_perf_query_counter kblgt2_memory_reads_query_counters[41]; static struct gen_perf_query_info kblgt2_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "57b59202-172b-477a-87de-33f85572c589", .counters = kblgt2_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_memory_writes_mux_regs[47]; static struct gen_perf_query_register_prog kblgt2_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog kblgt2_memory_writes_flex_regs[7]; static struct gen_perf_query_counter kblgt2_memory_writes_query_counters[41]; static struct gen_perf_query_info kblgt2_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0", .counters = kblgt2_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_compute_extended_mux_regs[72]; static struct gen_perf_query_register_prog kblgt2_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog kblgt2_compute_extended_flex_regs[7]; static struct gen_perf_query_counter kblgt2_compute_extended_query_counters[38]; static struct gen_perf_query_info kblgt2_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "4af0400a-81c3-47db-a6b6-deddbd75680e", .counters = kblgt2_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_compute_l3_cache_mux_regs[60]; static struct gen_perf_query_register_prog kblgt2_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog kblgt2_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter kblgt2_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info kblgt2_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "0e22f995-79ca-4f67-83ab-e9d9772488d8", .counters = kblgt2_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_hdc_and_sf_mux_regs[54]; static struct gen_perf_query_register_prog kblgt2_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog kblgt2_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter kblgt2_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info kblgt2_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937", .counters = kblgt2_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_l3_1_mux_regs[71]; static struct gen_perf_query_register_prog kblgt2_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog kblgt2_l3_1_flex_regs[7]; static struct gen_perf_query_counter kblgt2_l3_1_query_counters[39]; static struct gen_perf_query_info kblgt2_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "d2bbe790-f058-42d9-81c6-cdedcf655bc2", .counters = kblgt2_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_l3_2_mux_regs[44]; static struct gen_perf_query_register_prog kblgt2_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog kblgt2_l3_2_flex_regs[7]; static struct gen_perf_query_counter kblgt2_l3_2_query_counters[37]; static struct gen_perf_query_info kblgt2_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "2f8e32e4-5956-46e2-af31-c8ea95887332", .counters = kblgt2_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_l3_3_mux_regs[43]; static struct gen_perf_query_register_prog kblgt2_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog kblgt2_l3_3_flex_regs[7]; static struct gen_perf_query_counter kblgt2_l3_3_query_counters[37]; static struct gen_perf_query_info kblgt2_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "ca046aad-b5fb-4101-adce-6473ee6e5b14", .counters = kblgt2_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_rasterizer_and_pixel_backend_mux_regs[31]; static struct gen_perf_query_register_prog kblgt2_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog kblgt2_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter kblgt2_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info kblgt2_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "605f388f-24bb-455c-88e3-8d57ae0d7e9f", .counters = kblgt2_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_sampler_mux_regs[69]; static struct gen_perf_query_register_prog kblgt2_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog kblgt2_sampler_flex_regs[7]; static struct gen_perf_query_counter kblgt2_sampler_query_counters[41]; static struct gen_perf_query_info kblgt2_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af", .counters = kblgt2_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_tdl_1_mux_regs[68]; static struct gen_perf_query_register_prog kblgt2_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog kblgt2_tdl_1_flex_regs[7]; static struct gen_perf_query_counter kblgt2_tdl_1_query_counters[41]; static struct gen_perf_query_info kblgt2_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "105db928-5542-466b-9128-e1f3c91426cb", .counters = kblgt2_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_tdl_2_mux_regs[42]; static struct gen_perf_query_register_prog kblgt2_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog kblgt2_tdl_2_flex_regs[7]; static struct gen_perf_query_counter kblgt2_tdl_2_query_counters[41]; static struct gen_perf_query_info kblgt2_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "03db94d2-b37f-4c58-a791-0d2067b013bb", .counters = kblgt2_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_compute_extra_mux_regs[32]; static struct gen_perf_query_register_prog kblgt2_compute_extra_b_counter_regs[6]; static struct gen_perf_query_register_prog kblgt2_compute_extra_flex_regs[7]; static struct gen_perf_query_counter kblgt2_compute_extra_query_counters[5]; static struct gen_perf_query_info kblgt2_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16", .counters = kblgt2_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_compute_extra_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_compute_extra_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_vme_pipe_mux_regs[62]; static struct gen_perf_query_register_prog kblgt2_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog kblgt2_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter kblgt2_vme_pipe_query_counters[10]; static struct gen_perf_query_info kblgt2_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61", .counters = kblgt2_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt2_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14380002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06393000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A33F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C33F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A37A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C37A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06383000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900844 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_gpu_busyness_mux_regs[34]; static struct gen_perf_query_register_prog kblgt2_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter kblgt2_gpu_busyness_query_counters[8]; static struct gen_perf_query_info kblgt2_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "6c66fe6e-2988-454a-bfae-7fca3bbcbec2", .counters = kblgt2_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog kblgt2_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter kblgt2_test_oa_query_counters[12]; static struct gen_perf_query_info kblgt2_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9.5", .guid = "baa3c7e4-52b6-4b85-801e-465a94b746dd", .counters = kblgt2_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt2_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog kblgt2_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter kblgt2_pma__stall_query_counters[4]; static struct gen_perf_query_info kblgt2_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "b49aa434-4958-4d98-9e6f-443ff27ca74d", .counters = kblgt2_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt2_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt2_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void kblgt2_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt2_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt2__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt2__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt2__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_kblgt2(struct gen_perf *perf) { kblgt2_register_render_basic_counter_query(perf); kblgt2_register_compute_basic_counter_query(perf); kblgt2_register_render_pipe_profile_counter_query(perf); kblgt2_register_memory_reads_counter_query(perf); kblgt2_register_memory_writes_counter_query(perf); kblgt2_register_compute_extended_counter_query(perf); kblgt2_register_compute_l3_cache_counter_query(perf); kblgt2_register_hdc_and_sf_counter_query(perf); kblgt2_register_l3_1_counter_query(perf); kblgt2_register_l3_2_counter_query(perf); kblgt2_register_l3_3_counter_query(perf); kblgt2_register_rasterizer_and_pixel_backend_counter_query(perf); kblgt2_register_sampler_counter_query(perf); kblgt2_register_tdl_1_counter_query(perf); kblgt2_register_tdl_2_counter_query(perf); kblgt2_register_compute_extra_counter_query(perf); kblgt2_register_vme_pipe_counter_query(perf); kblgt2_register_gpu_busyness_counter_query(perf); kblgt2_register_test_oa_counter_query(perf); kblgt2_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog kblgt3_render_basic_mux_regs[83]; static struct gen_perf_query_register_prog kblgt3_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog kblgt3_render_basic_flex_regs[7]; static struct gen_perf_query_counter kblgt3_render_basic_query_counters[52]; static struct gen_perf_query_info kblgt3_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "17b4f3e0-d578-4ae3-b7a8-98d756d1e0df", .counters = kblgt3_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CA200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51902240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900242 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57902220 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53902222 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_compute_basic_mux_regs[78]; static struct gen_perf_query_register_prog kblgt3_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog kblgt3_compute_basic_flex_regs[7]; static struct gen_perf_query_counter kblgt3_compute_basic_query_counters[39]; static struct gen_perf_query_info kblgt3_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "9823aaa1-b06f-40ce-884b-cd798c79f0c2", .counters = kblgt3_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_render_pipe_profile_mux_regs[114]; static struct gen_perf_query_register_prog kblgt3_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog kblgt3_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter kblgt3_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info kblgt3_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "c7c735f3-ce58-45cf-aa04-30b183f1faff", .counters = kblgt3_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_memory_reads_mux_regs[47]; static struct gen_perf_query_register_prog kblgt3_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog kblgt3_memory_reads_flex_regs[7]; static struct gen_perf_query_counter kblgt3_memory_reads_query_counters[41]; static struct gen_perf_query_info kblgt3_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "96ec2219-040b-428a-856a-6bc03363a057", .counters = kblgt3_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_memory_writes_mux_regs[47]; static struct gen_perf_query_register_prog kblgt3_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog kblgt3_memory_writes_flex_regs[7]; static struct gen_perf_query_counter kblgt3_memory_writes_query_counters[41]; static struct gen_perf_query_info kblgt3_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "03372b64-4996-4d3b-aa18-790e75eeb9c2", .counters = kblgt3_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_compute_extended_mux_regs[72]; static struct gen_perf_query_register_prog kblgt3_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog kblgt3_compute_extended_flex_regs[7]; static struct gen_perf_query_counter kblgt3_compute_extended_query_counters[38]; static struct gen_perf_query_info kblgt3_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150", .counters = kblgt3_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_compute_l3_cache_mux_regs[60]; static struct gen_perf_query_register_prog kblgt3_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog kblgt3_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter kblgt3_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info kblgt3_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "2ce0911a-27fc-4887-96f0-11084fa807c3", .counters = kblgt3_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_hdc_and_sf_mux_regs[54]; static struct gen_perf_query_register_prog kblgt3_hdc_and_sf_b_counter_regs[9]; static struct gen_perf_query_register_prog kblgt3_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter kblgt3_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info kblgt3_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "546c4c1d-99b8-42fb-a107-5aaabb5314a8", .counters = kblgt3_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_l3_1_mux_regs[71]; static struct gen_perf_query_register_prog kblgt3_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog kblgt3_l3_1_flex_regs[7]; static struct gen_perf_query_counter kblgt3_l3_1_query_counters[39]; static struct gen_perf_query_info kblgt3_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "4e93d156-9b39-4268-8544-a8e0480806d7", .counters = kblgt3_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_l3_2_mux_regs[44]; static struct gen_perf_query_register_prog kblgt3_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog kblgt3_l3_2_flex_regs[7]; static struct gen_perf_query_counter kblgt3_l3_2_query_counters[37]; static struct gen_perf_query_info kblgt3_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "de1bec86-ca92-4b43-89fa-147653221cc0", .counters = kblgt3_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_l3_3_mux_regs[43]; static struct gen_perf_query_register_prog kblgt3_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog kblgt3_l3_3_flex_regs[7]; static struct gen_perf_query_counter kblgt3_l3_3_query_counters[37]; static struct gen_perf_query_info kblgt3_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef", .counters = kblgt3_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_rasterizer_and_pixel_backend_mux_regs[31]; static struct gen_perf_query_register_prog kblgt3_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog kblgt3_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter kblgt3_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info kblgt3_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281", .counters = kblgt3_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_sampler_mux_regs[69]; static struct gen_perf_query_register_prog kblgt3_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog kblgt3_sampler_flex_regs[7]; static struct gen_perf_query_counter kblgt3_sampler_query_counters[41]; static struct gen_perf_query_info kblgt3_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda", .counters = kblgt3_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_tdl_1_mux_regs[68]; static struct gen_perf_query_register_prog kblgt3_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog kblgt3_tdl_1_flex_regs[7]; static struct gen_perf_query_counter kblgt3_tdl_1_query_counters[41]; static struct gen_perf_query_info kblgt3_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "469a05e5-e299-46f7-9598-7b05f3c34991", .counters = kblgt3_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_tdl_2_mux_regs[42]; static struct gen_perf_query_register_prog kblgt3_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog kblgt3_tdl_2_flex_regs[7]; static struct gen_perf_query_counter kblgt3_tdl_2_query_counters[41]; static struct gen_perf_query_info kblgt3_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "52f925c6-786a-4ec6-86ce-cba85c83453a", .counters = kblgt3_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_compute_extra_mux_regs[69]; static struct gen_perf_query_counter kblgt3_compute_extra_query_counters[5]; static struct gen_perf_query_info kblgt3_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "efc497ac-884e-4ee4-a4a8-15fba22aaf21", .counters = kblgt3_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_vme_pipe_mux_regs[73]; static struct gen_perf_query_register_prog kblgt3_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog kblgt3_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter kblgt3_vme_pipe_query_counters[10]; static struct gen_perf_query_info kblgt3_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917", .counters = kblgt3_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = kblgt3_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x479008A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_gpu_busyness_mux_regs[42]; static struct gen_perf_query_register_prog kblgt3_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter kblgt3_gpu_busyness_query_counters[9]; static struct gen_perf_query_info kblgt3_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "b55ecba1-2aa9-422e-89ff-b9e30f03d447", .counters = kblgt3_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19D05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00085 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25D00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__gpu_busyness__vdbox1_busy__read; counter->name = "Vdbox1 Ring Busy"; counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog kblgt3_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter kblgt3_test_oa_query_counters[12]; static struct gen_perf_query_info kblgt3_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "f1792f32-6db2-4b50-b4b2-557128f1688d", .counters = kblgt3_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog kblgt3_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog kblgt3_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter kblgt3_pma__stall_query_counters[4]; static struct gen_perf_query_info kblgt3_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "85bc2e4f-2563-4388-921b-dc0dad879cf3", .counters = kblgt3_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = kblgt3_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = kblgt3_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void kblgt3_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &kblgt3_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = kblgt3__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = kblgt3__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = kblgt3__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_kblgt3(struct gen_perf *perf) { kblgt3_register_render_basic_counter_query(perf); kblgt3_register_compute_basic_counter_query(perf); kblgt3_register_render_pipe_profile_counter_query(perf); kblgt3_register_memory_reads_counter_query(perf); kblgt3_register_memory_writes_counter_query(perf); kblgt3_register_compute_extended_counter_query(perf); kblgt3_register_compute_l3_cache_counter_query(perf); kblgt3_register_hdc_and_sf_counter_query(perf); kblgt3_register_l3_1_counter_query(perf); kblgt3_register_l3_2_counter_query(perf); kblgt3_register_l3_3_counter_query(perf); kblgt3_register_rasterizer_and_pixel_backend_counter_query(perf); kblgt3_register_sampler_counter_query(perf); kblgt3_register_tdl_1_counter_query(perf); kblgt3_register_tdl_2_counter_query(perf); kblgt3_register_compute_extra_counter_query(perf); kblgt3_register_vme_pipe_counter_query(perf); kblgt3_register_gpu_busyness_counter_query(perf); kblgt3_register_test_oa_counter_query(perf); kblgt3_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog cflgt2_render_basic_mux_regs[70]; static struct gen_perf_query_register_prog cflgt2_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog cflgt2_render_basic_flex_regs[7]; static struct gen_perf_query_counter cflgt2_render_basic_query_counters[52]; static struct gen_perf_query_info cflgt2_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "7fa796a4-0c7a-4201-afc6-cff0b2f528a2", .counters = cflgt2_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C2200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51904400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_compute_basic_mux_regs[78]; static struct gen_perf_query_register_prog cflgt2_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog cflgt2_compute_basic_flex_regs[7]; static struct gen_perf_query_counter cflgt2_compute_basic_query_counters[39]; static struct gen_perf_query_info cflgt2_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "dc8cf7ea-26b4-4478-ac93-dab174f92ac0", .counters = cflgt2_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_render_pipe_profile_mux_regs[114]; static struct gen_perf_query_register_prog cflgt2_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog cflgt2_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter cflgt2_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info cflgt2_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "2221e4d5-ed7b-445e-b2cc-3de1b97f4d42", .counters = cflgt2_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_memory_reads_mux_regs[47]; static struct gen_perf_query_register_prog cflgt2_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog cflgt2_memory_reads_flex_regs[7]; static struct gen_perf_query_counter cflgt2_memory_reads_query_counters[41]; static struct gen_perf_query_info cflgt2_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "82096a90-e2fa-4f38-ac14-562b2496933a", .counters = cflgt2_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_memory_writes_mux_regs[47]; static struct gen_perf_query_register_prog cflgt2_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog cflgt2_memory_writes_flex_regs[7]; static struct gen_perf_query_counter cflgt2_memory_writes_query_counters[41]; static struct gen_perf_query_info cflgt2_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "9f638880-02e9-4a8d-896a-7670a3bf0d35", .counters = cflgt2_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_compute_extended_mux_regs[72]; static struct gen_perf_query_register_prog cflgt2_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog cflgt2_compute_extended_flex_regs[7]; static struct gen_perf_query_counter cflgt2_compute_extended_query_counters[38]; static struct gen_perf_query_info cflgt2_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "8d4ad934-7c16-43d5-845a-51067a4c8e2f", .counters = cflgt2_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_compute_l3_cache_mux_regs[60]; static struct gen_perf_query_register_prog cflgt2_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog cflgt2_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter cflgt2_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info cflgt2_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "4389cf07-1424-4963-b2d2-64fcec75406d", .counters = cflgt2_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_hdc_and_sf_mux_regs[54]; static struct gen_perf_query_register_prog cflgt2_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog cflgt2_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter cflgt2_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info cflgt2_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "1c003bbe-ca7f-49d0-bb0f-2f0096147a00", .counters = cflgt2_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_l3_1_mux_regs[71]; static struct gen_perf_query_register_prog cflgt2_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog cflgt2_l3_1_flex_regs[7]; static struct gen_perf_query_counter cflgt2_l3_1_query_counters[39]; static struct gen_perf_query_info cflgt2_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "2a208cb2-0f82-4518-844d-c4c4699659a1", .counters = cflgt2_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_l3_2_mux_regs[44]; static struct gen_perf_query_register_prog cflgt2_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog cflgt2_l3_2_flex_regs[7]; static struct gen_perf_query_counter cflgt2_l3_2_query_counters[37]; static struct gen_perf_query_info cflgt2_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "bf38efc7-7a5c-4cc9-87ff-cbb4b954b4ec", .counters = cflgt2_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_l3_3_mux_regs[43]; static struct gen_perf_query_register_prog cflgt2_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog cflgt2_l3_3_flex_regs[7]; static struct gen_perf_query_counter cflgt2_l3_3_query_counters[37]; static struct gen_perf_query_info cflgt2_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "a9cf8100-606e-4cb1-a509-e69f8588c050", .counters = cflgt2_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_rasterizer_and_pixel_backend_mux_regs[31]; static struct gen_perf_query_register_prog cflgt2_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog cflgt2_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter cflgt2_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info cflgt2_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "4905b811-fbb0-4f51-aacd-3d46555aad3d", .counters = cflgt2_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_sampler_mux_regs[69]; static struct gen_perf_query_register_prog cflgt2_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog cflgt2_sampler_flex_regs[7]; static struct gen_perf_query_counter cflgt2_sampler_query_counters[41]; static struct gen_perf_query_info cflgt2_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "00defd09-c283-4d34-a3c5-e2c4f9120adf", .counters = cflgt2_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_tdl_1_mux_regs[68]; static struct gen_perf_query_register_prog cflgt2_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog cflgt2_tdl_1_flex_regs[7]; static struct gen_perf_query_counter cflgt2_tdl_1_query_counters[41]; static struct gen_perf_query_info cflgt2_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "87b33db5-ad38-4a08-a9e7-5f807dee1a45", .counters = cflgt2_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_tdl_2_mux_regs[42]; static struct gen_perf_query_register_prog cflgt2_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog cflgt2_tdl_2_flex_regs[7]; static struct gen_perf_query_counter cflgt2_tdl_2_query_counters[41]; static struct gen_perf_query_info cflgt2_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "fbf2fbc7-c1ce-4b7a-8f32-cf60eb947fa5", .counters = cflgt2_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_compute_extra_mux_regs[32]; static struct gen_perf_query_register_prog cflgt2_compute_extra_b_counter_regs[6]; static struct gen_perf_query_register_prog cflgt2_compute_extra_flex_regs[7]; static struct gen_perf_query_counter cflgt2_compute_extra_query_counters[5]; static struct gen_perf_query_info cflgt2_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "5f679fb0-909e-4c0e-b4b2-8e801f83e71b", .counters = cflgt2_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_compute_extra_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_compute_extra_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_vme_pipe_mux_regs[62]; static struct gen_perf_query_register_prog cflgt2_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog cflgt2_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter cflgt2_vme_pipe_query_counters[10]; static struct gen_perf_query_info cflgt2_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "0d09ba9a-1d1c-457d-83e2-74ac448014d6", .counters = cflgt2_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt2_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14380002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06393000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A33F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C33F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A37A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C37A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06383000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900844 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_gpu_busyness_mux_regs[34]; static struct gen_perf_query_register_prog cflgt2_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter cflgt2_gpu_busyness_query_counters[8]; static struct gen_perf_query_info cflgt2_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "e2f162ae-5732-4af0-8b11-69510f57094a", .counters = cflgt2_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog cflgt2_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter cflgt2_test_oa_query_counters[12]; static struct gen_perf_query_info cflgt2_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9.5", .guid = "74fb4902-d3d3-4237-9e90-cbdc68d0a446", .counters = cflgt2_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt2_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog cflgt2_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter cflgt2_pma__stall_query_counters[4]; static struct gen_perf_query_info cflgt2_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "5ccbf9fb-6bf2-456b-a749-bdff7b1aff13", .counters = cflgt2_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt2_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt2_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cflgt2_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt2_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt2__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt2__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt2__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_cflgt2(struct gen_perf *perf) { cflgt2_register_render_basic_counter_query(perf); cflgt2_register_compute_basic_counter_query(perf); cflgt2_register_render_pipe_profile_counter_query(perf); cflgt2_register_memory_reads_counter_query(perf); cflgt2_register_memory_writes_counter_query(perf); cflgt2_register_compute_extended_counter_query(perf); cflgt2_register_compute_l3_cache_counter_query(perf); cflgt2_register_hdc_and_sf_counter_query(perf); cflgt2_register_l3_1_counter_query(perf); cflgt2_register_l3_2_counter_query(perf); cflgt2_register_l3_3_counter_query(perf); cflgt2_register_rasterizer_and_pixel_backend_counter_query(perf); cflgt2_register_sampler_counter_query(perf); cflgt2_register_tdl_1_counter_query(perf); cflgt2_register_tdl_2_counter_query(perf); cflgt2_register_compute_extra_counter_query(perf); cflgt2_register_vme_pipe_counter_query(perf); cflgt2_register_gpu_busyness_counter_query(perf); cflgt2_register_test_oa_counter_query(perf); cflgt2_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog cflgt3_render_basic_mux_regs[83]; static struct gen_perf_query_register_prog cflgt3_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog cflgt3_render_basic_flex_regs[7]; static struct gen_perf_query_counter cflgt3_render_basic_query_counters[52]; static struct gen_perf_query_info cflgt3_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "b316bcab-212f-4228-97de-af6b5a1a2ea1", .counters = cflgt3_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CA200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51902240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900242 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57902220 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53902222 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_compute_basic_mux_regs[78]; static struct gen_perf_query_register_prog cflgt3_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog cflgt3_compute_basic_flex_regs[7]; static struct gen_perf_query_counter cflgt3_compute_basic_query_counters[39]; static struct gen_perf_query_info cflgt3_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "607f9cc8-e026-4d5f-bfad-45c77eabc150", .counters = cflgt3_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_render_pipe_profile_mux_regs[114]; static struct gen_perf_query_register_prog cflgt3_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog cflgt3_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter cflgt3_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info cflgt3_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "9875e050-b1bc-45e6-a6ab-665594601df9", .counters = cflgt3_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_memory_reads_mux_regs[47]; static struct gen_perf_query_register_prog cflgt3_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog cflgt3_memory_reads_flex_regs[7]; static struct gen_perf_query_counter cflgt3_memory_reads_query_counters[41]; static struct gen_perf_query_info cflgt3_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "49c65f34-e625-4ca4-86b7-88693e624d4c", .counters = cflgt3_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_memory_writes_mux_regs[47]; static struct gen_perf_query_register_prog cflgt3_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog cflgt3_memory_writes_flex_regs[7]; static struct gen_perf_query_counter cflgt3_memory_writes_query_counters[41]; static struct gen_perf_query_info cflgt3_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "45c9e8ee-2998-4d83-88e8-9cb7e03287bf", .counters = cflgt3_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_compute_extended_mux_regs[72]; static struct gen_perf_query_register_prog cflgt3_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog cflgt3_compute_extended_flex_regs[7]; static struct gen_perf_query_counter cflgt3_compute_extended_query_counters[38]; static struct gen_perf_query_info cflgt3_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "bac415ce-d7a2-4f8d-9b16-834deba7330e", .counters = cflgt3_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_compute_l3_cache_mux_regs[60]; static struct gen_perf_query_register_prog cflgt3_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog cflgt3_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter cflgt3_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info cflgt3_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "a8cfca44-0e74-4338-9e57-3daad98957dd", .counters = cflgt3_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_hdc_and_sf_mux_regs[54]; static struct gen_perf_query_register_prog cflgt3_hdc_and_sf_b_counter_regs[9]; static struct gen_perf_query_register_prog cflgt3_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter cflgt3_hdc_and_sf_query_counters[39]; static struct gen_perf_query_info cflgt3_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "3d9acca5-8d39-4c34-89ee-f921848d8562", .counters = cflgt3_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss2)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_l3_1_mux_regs[71]; static struct gen_perf_query_register_prog cflgt3_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog cflgt3_l3_1_flex_regs[7]; static struct gen_perf_query_counter cflgt3_l3_1_query_counters[39]; static struct gen_perf_query_info cflgt3_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "93e582ea-de69-46e3-81b5-73386164c047", .counters = cflgt3_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_l3_2_mux_regs[44]; static struct gen_perf_query_register_prog cflgt3_l3_2_b_counter_regs[14]; static struct gen_perf_query_register_prog cflgt3_l3_2_flex_regs[7]; static struct gen_perf_query_counter cflgt3_l3_2_query_counters[37]; static struct gen_perf_query_info cflgt3_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "6e3680f3-8347-4e26-b930-3900d18d1322", .counters = cflgt3_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_l3_3_mux_regs[43]; static struct gen_perf_query_register_prog cflgt3_l3_3_b_counter_regs[14]; static struct gen_perf_query_register_prog cflgt3_l3_3_flex_regs[7]; static struct gen_perf_query_counter cflgt3_l3_3_query_counters[37]; static struct gen_perf_query_info cflgt3_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_3", .guid = "1f513186-11d6-422d-a879-be86f2d08414", .counters = cflgt3_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__l30_bank3_stalled__read; counter->name = "Slice0 L3 Bank3 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__l3_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_rasterizer_and_pixel_backend_mux_regs[31]; static struct gen_perf_query_register_prog cflgt3_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog cflgt3_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter cflgt3_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info cflgt3_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "d37d4266-b749-48b2-9652-c24b91784fc6", .counters = cflgt3_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_sampler_mux_regs[69]; static struct gen_perf_query_register_prog cflgt3_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog cflgt3_sampler_flex_regs[7]; static struct gen_perf_query_counter cflgt3_sampler_query_counters[41]; static struct gen_perf_query_info cflgt3_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "5951c1d7-feef-4981-b0b5-4e4983023119", .counters = cflgt3_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_tdl_1_mux_regs[68]; static struct gen_perf_query_register_prog cflgt3_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog cflgt3_tdl_1_flex_regs[7]; static struct gen_perf_query_counter cflgt3_tdl_1_query_counters[41]; static struct gen_perf_query_info cflgt3_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "bf279ed6-b3dd-43f3-9810-cb55cb78fc62", .counters = cflgt3_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_tdl_2_mux_regs[42]; static struct gen_perf_query_register_prog cflgt3_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog cflgt3_tdl_2_flex_regs[7]; static struct gen_perf_query_counter cflgt3_tdl_2_query_counters[41]; static struct gen_perf_query_info cflgt3_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "a70c3fa2-e705-4f5a-8883-2ebd0feef1d2", .counters = cflgt3_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_compute_extra_mux_regs[69]; static struct gen_perf_query_counter cflgt3_compute_extra_query_counters[5]; static struct gen_perf_query_info cflgt3_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "e61ae394-9d9e-4204-a735-1dad7e44d953", .counters = cflgt3_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_vme_pipe_mux_regs[73]; static struct gen_perf_query_register_prog cflgt3_vme_pipe_b_counter_regs[17]; static struct gen_perf_query_register_prog cflgt3_vme_pipe_flex_regs[2]; static struct gen_perf_query_counter cflgt3_vme_pipe_query_counters[10]; static struct gen_perf_query_info cflgt3_vme_pipe_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Media Vme Pipe Gen9", .guid = "94272ad9-45ee-4e34-b7a7-51546cd6405c", .counters = cflgt3_vme_pipe_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_vme_pipe_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_vme_pipe_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cflgt3_vme_pipe_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_vme_pipe_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_vme_pipe_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x479008A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__vme_pipe__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__vme_pipe__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__vme_pipe__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__vme_pipe__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__vme_pipe__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__vme_pipe__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__vme_pipe__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__vme_pipe__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__vme_pipe__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__vme_pipe__vme_busy__read; counter->name = "VME Busy"; counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__vme_pipe__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_gpu_busyness_mux_regs[42]; static struct gen_perf_query_register_prog cflgt3_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter cflgt3_gpu_busyness_query_counters[9]; static struct gen_perf_query_info cflgt3_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "22b7e0c2-cade-425f-b099-34479768c72a", .counters = cflgt3_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19D05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00085 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25D00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__gpu_busyness__vdbox1_busy__read; counter->name = "Vdbox1 Ring Busy"; counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_test_oa_mux_regs[13]; static struct gen_perf_query_register_prog cflgt3_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter cflgt3_test_oa_query_counters[12]; static struct gen_perf_query_info cflgt3_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "577e8e2c-3fa0-4875-8743-3538d585e3b0", .counters = cflgt3_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cflgt3_pma__stall_mux_regs[24]; static struct gen_perf_query_register_prog cflgt3_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter cflgt3_pma__stall_query_counters[4]; static struct gen_perf_query_info cflgt3_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "c11af8d1-858b-4f8b-98fb-8d683ba8bda0", .counters = cflgt3_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cflgt3_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cflgt3_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cflgt3_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cflgt3_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0FAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D16A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D162E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cflgt3__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cflgt3__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cflgt3__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_cflgt3(struct gen_perf *perf) { cflgt3_register_render_basic_counter_query(perf); cflgt3_register_compute_basic_counter_query(perf); cflgt3_register_render_pipe_profile_counter_query(perf); cflgt3_register_memory_reads_counter_query(perf); cflgt3_register_memory_writes_counter_query(perf); cflgt3_register_compute_extended_counter_query(perf); cflgt3_register_compute_l3_cache_counter_query(perf); cflgt3_register_hdc_and_sf_counter_query(perf); cflgt3_register_l3_1_counter_query(perf); cflgt3_register_l3_2_counter_query(perf); cflgt3_register_l3_3_counter_query(perf); cflgt3_register_rasterizer_and_pixel_backend_counter_query(perf); cflgt3_register_sampler_counter_query(perf); cflgt3_register_tdl_1_counter_query(perf); cflgt3_register_tdl_2_counter_query(perf); cflgt3_register_compute_extra_counter_query(perf); cflgt3_register_vme_pipe_counter_query(perf); cflgt3_register_gpu_busyness_counter_query(perf); cflgt3_register_test_oa_counter_query(perf); cflgt3_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog bxt_render_basic_mux_regs[80]; static struct gen_perf_query_register_prog bxt_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog bxt_render_basic_flex_regs[7]; static struct gen_perf_query_counter bxt_render_basic_query_counters[52]; static struct gen_perf_query_info bxt_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a", .counters = bxt_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.revision >= 0x03) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C00F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FCC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00101000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04101000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08120021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00141000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08141000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04302000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08320840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08344000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D931831 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F939F3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01939E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x039303BC }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901110 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900423 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59901111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_compute_basic_mux_regs[72]; static struct gen_perf_query_register_prog bxt_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog bxt_compute_basic_flex_regs[7]; static struct gen_perf_query_counter bxt_compute_basic_query_counters[39]; static struct gen_perf_query_info bxt_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "012d72cf-82a9-4d25-8ddf-74076fd30797", .counters = bxt_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E1400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0114 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F6B42 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F6200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F4100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F6C4C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F8800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F08A2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C1451 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938A28 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900178 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900125 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900123 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_render_pipe_profile_mux_regs[94]; static struct gen_perf_query_register_prog bxt_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog bxt_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter bxt_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info bxt_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "ce416533-e49e-4211-80af-ec513590a914", .counters = bxt_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10186800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13820020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178703E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09810200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B810030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03810003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21819140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23819050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03820D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11820000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0182C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F831000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848072 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09860092 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01869100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F870065 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B952000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D955055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951455 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0992A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1192A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392028A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B92A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900863 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C22 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_memory_reads_mux_regs[44]; static struct gen_perf_query_register_prog bxt_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog bxt_memory_reads_flex_regs[7]; static struct gen_perf_query_counter bxt_memory_reads_query_counters[41]; static struct gen_perf_query_info bxt_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "398e2452-18d7-42d0-b241-e4d0a9148ada", .counters = bxt_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900170 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900171 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900172 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900173 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900174 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900175 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900176 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90017F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_memory_writes_mux_regs[44]; static struct gen_perf_query_register_prog bxt_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog bxt_memory_writes_flex_regs[7]; static struct gen_perf_query_counter bxt_memory_writes_query_counters[41]; static struct gen_perf_query_info bxt_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5", .counters = bxt_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900181 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900182 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900183 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900184 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900185 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900186 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900170 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_compute_extended_mux_regs[93]; static struct gen_perf_query_register_prog bxt_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog bxt_compute_extended_flex_regs[7]; static struct gen_perf_query_counter bxt_compute_extended_query_counters[38]; static struct gen_perf_query_info bxt_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "caf3596a-7bb1-4dec-b3b3-2a080d283b49", .counters = bxt_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B41 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F404C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C1900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C1A33 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C1B35 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C3337 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C31C7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA8AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C6AAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C2950 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_compute_l3_cache_mux_regs[68]; static struct gen_perf_query_register_prog bxt_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog bxt_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter bxt_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info bxt_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527", .counters = bxt_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C03B0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F4001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C4015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03931980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A00A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900178 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_hdc_and_sf_mux_regs[42]; static struct gen_perf_query_register_prog bxt_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog bxt_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter bxt_hdc_and_sf_query_counters[38]; static struct gen_perf_query_info bxt_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a", .counters = bxt_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F6100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F416B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13920200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_l3_1_mux_regs[154]; static struct gen_perf_query_register_prog bxt_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog bxt_l3_1_flex_regs[7]; static struct gen_perf_query_counter bxt_l3_1_query_counters[39]; static struct gen_perf_query_info bxt_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "00ad5a41-7eab-4f7a-9103-49d411c67219", .counters = bxt_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.revision >= 0x03) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12643400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12653400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C6800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F1554 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A640024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10640000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04640000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C650024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; } if (perf->sys_vars.revision < 0x03) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14640340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14650340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C6800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F1554 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04642400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22640000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A640000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06650024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_rasterizer_and_pixel_backend_mux_regs[41]; static struct gen_perf_query_register_prog bxt_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog bxt_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter bxt_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info bxt_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b", .counters = bxt_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D7800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D79E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100E3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D802F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040E0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060F0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_sampler_mux_regs[93]; static struct gen_perf_query_register_prog bxt_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog bxt_sampler_flex_regs[7]; static struct gen_perf_query_counter bxt_sampler_query_counters[41]; static struct gen_perf_query_info bxt_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "8364e2a8-af63-40af-b0d5-42969a255654", .counters = bxt_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141600AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143600AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145600AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E01A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0065 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F023F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2CC030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04132180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E142000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E150140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C163000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E160068 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A164000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04330043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02330000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0234A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02363460 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08364000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06530043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02530000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E563000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00563400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C564000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9014A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_tdl_1_mux_regs[86]; static struct gen_perf_query_register_prog bxt_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog bxt_tdl_1_flex_regs[7]; static struct gen_perf_query_counter bxt_tdl_1_query_counters[41]; static struct gen_perf_query_info bxt_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92", .counters = bxt_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0BC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0302 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C00F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A31E5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150054 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A3280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E350140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18360028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5A3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A3280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_tdl_2_mux_regs[58]; static struct gen_perf_query_register_prog bxt_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog bxt_tdl_2_flex_regs[7]; static struct gen_perf_query_counter bxt_tdl_2_query_counters[41]; static struct gen_perf_query_info bxt_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "d260f03f-b34d-4b49-a44e-436819117332", .counters = bxt_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A026B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0173 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A026B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0069 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F030A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A37E7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A3380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A006F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A352000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A37E7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0254A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_compute_extra_mux_regs[37]; static struct gen_perf_query_register_prog bxt_compute_extra_b_counter_regs[6]; static struct gen_perf_query_register_prog bxt_compute_extra_flex_regs[7]; static struct gen_perf_query_counter bxt_compute_extra_query_counters[5]; static struct gen_perf_query_info bxt_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a", .counters = bxt_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_compute_extra_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = bxt_compute_extra_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void bxt_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06142000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A3180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_gpu_busyness_mux_regs[30]; static struct gen_perf_query_register_prog bxt_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter bxt_gpu_busyness_query_counters[8]; static struct gen_perf_query_info bxt_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "c9f5fa3a-d14f-400c-a89a-211206b00ee7", .counters = bxt_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void bxt_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23810008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B934000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09948000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950085 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11950000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B924000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900442 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_test_oa_mux_regs[12]; static struct gen_perf_query_register_prog bxt_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter bxt_test_oa_query_counters[12]; static struct gen_perf_query_info bxt_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "5ee72f5c-092f-421e-8b70-225f7c3e9612", .counters = bxt_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void bxt_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23810008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog bxt_pma__stall_mux_regs[34]; static struct gen_perf_query_register_prog bxt_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter bxt_pma__stall_query_counters[4]; static struct gen_perf_query_info bxt_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "d49cd0d8-8c7f-4465-94fc-51e08c9050bc", .counters = bxt_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = bxt_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = bxt_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void bxt_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &bxt_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C0045 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C2300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C26C4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C264E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x199300AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = bxt__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = bxt__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = bxt__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_bxt(struct gen_perf *perf) { bxt_register_render_basic_counter_query(perf); bxt_register_compute_basic_counter_query(perf); bxt_register_render_pipe_profile_counter_query(perf); bxt_register_memory_reads_counter_query(perf); bxt_register_memory_writes_counter_query(perf); bxt_register_compute_extended_counter_query(perf); bxt_register_compute_l3_cache_counter_query(perf); bxt_register_hdc_and_sf_counter_query(perf); bxt_register_l3_1_counter_query(perf); bxt_register_rasterizer_and_pixel_backend_counter_query(perf); bxt_register_sampler_counter_query(perf); bxt_register_tdl_1_counter_query(perf); bxt_register_tdl_2_counter_query(perf); bxt_register_compute_extra_counter_query(perf); bxt_register_gpu_busyness_counter_query(perf); bxt_register_test_oa_counter_query(perf); bxt_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog glk_render_basic_mux_regs[80]; static struct gen_perf_query_register_prog glk_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog glk_render_basic_flex_regs[7]; static struct gen_perf_query_counter glk_render_basic_query_counters[52]; static struct gen_perf_query_info glk_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen9", .guid = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68", .counters = glk_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C00F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FCC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00101000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04101000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08120021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00141000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08141000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02308000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04302000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08318000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08320840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08344000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D931831 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F939F3F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01939E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x039303BC }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901110 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900423 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59901111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__sampler1_bottleneck__read; counter->name = "Sampler 1 Bottleneck"; counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__sampler0_busy__read; counter->name = "Sampler 0 Busy"; counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 0x12) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__sampler1_busy__read; counter->name = "Sampler 1 Busy"; counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 0x09) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__sampler0_bottleneck__read; counter->name = "Sampler 0 Bottleneck"; counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_hdc_lookups_throughput__read; counter->name = "GTI HDC TLB Lookup Throughput"; counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 376; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_compute_basic_mux_regs[72]; static struct gen_perf_query_register_prog glk_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog glk_compute_basic_flex_regs[7]; static struct gen_perf_query_counter glk_compute_basic_query_counters[39]; static struct gen_perf_query_info glk_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen9", .guid = "814285f6-354d-41d2-ba49-e24e622714a0", .counters = glk_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E1400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0114 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F6B42 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F6200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F4100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F6C4C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F8800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F08A2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C1451 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938A28 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900178 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900125 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900123 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_render_pipe_profile_mux_regs[94]; static struct gen_perf_query_register_prog glk_render_pipe_profile_b_counter_regs[21]; static struct gen_perf_query_register_prog glk_render_pipe_profile_flex_regs[7]; static struct gen_perf_query_counter glk_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info glk_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen9", .guid = "07d397a6-b3e6-49f6-9433-a4f293d55978", .counters = glk_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10186800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15810013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13820020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178703E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06174000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05804000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09810200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B810030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03810003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21819140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23819050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03820D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11820000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0182C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09824000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F831000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848072 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09844000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F848000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09860092 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01869100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F870065 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B952000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D955055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951455 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0992A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1192A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392028A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B92A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C01 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900863 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C22 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_memory_reads_mux_regs[44]; static struct gen_perf_query_register_prog glk_memory_reads_b_counter_regs[32]; static struct gen_perf_query_register_prog glk_memory_reads_flex_regs[7]; static struct gen_perf_query_counter glk_memory_reads_query_counters[41]; static struct gen_perf_query_info glk_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen9", .guid = "1a356946-5428-450b-a2f0-89f8783a302d", .counters = glk_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900170 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900171 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900172 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900173 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900174 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900175 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900176 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90017F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank3_reads__read; counter->name = "GtiL3Bank3Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_memory_writes_mux_regs[44]; static struct gen_perf_query_register_prog glk_memory_writes_b_counter_regs[32]; static struct gen_perf_query_register_prog glk_memory_writes_flex_regs[7]; static struct gen_perf_query_counter glk_memory_writes_query_counters[41]; static struct gen_perf_query_info glk_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen9", .guid = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9", .counters = glk_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900181 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900182 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900183 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900184 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900185 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900186 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900187 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900170 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all GTI accesses to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank3_writes__read; counter->name = "GtiL3Bank3Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_compute_extended_mux_regs[93]; static struct gen_perf_query_register_prog glk_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog glk_compute_extended_flex_regs[7]; static struct gen_perf_query_counter glk_compute_extended_query_counters[38]; static struct gen_perf_query_info glk_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen9", .guid = "bc9bcff2-459a-4cbc-986d-a84b077153f3", .counters = glk_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C0160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5515 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B41 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F4200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F404C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C1900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C1A33 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C1B35 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C3337 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C31C7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA8AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C6AAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C2950 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AAAA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_compute_l3_cache_mux_regs[68]; static struct gen_perf_query_register_prog glk_compute_l3_cache_b_counter_regs[13]; static struct gen_perf_query_register_prog glk_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter glk_compute_l3_cache_query_counters[54]; static struct gen_perf_query_info glk_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen9", .guid = "88ec931f-5b4a-453a-9db6-a61232b6143d", .counters = glk_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C03B0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E1500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F4001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C4015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03931980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A00A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900178 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank03_accesses__read; counter->name = "L3 Bank 03 Accesses"; counter->desc = "The total number of accesses to L3 Bank 03."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank00_accesses__read; counter->name = "L3 Bank 00 Accesses"; counter->desc = "The total number of accesses to L3 Bank 00."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank00_ic_accesses__read; counter->name = "L3 Bank 00 IC Accesses"; counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; } if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank00_ic_hits__read; counter->name = "L3 Bank 00 IC Hits"; counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank01_accesses__read; counter->name = "L3 Bank 01 Accesses"; counter->desc = "The total number of accesses to L3 Bank 01."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 300; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.slice_mask & 0x01) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank02_accesses__read; counter->name = "L3 Bank 02 Accesses"; counter->desc = "The total number of accesses to L3 Bank 02."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 380; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_hdc_and_sf_mux_regs[42]; static struct gen_perf_query_register_prog glk_hdc_and_sf_b_counter_regs[8]; static struct gen_perf_query_register_prog glk_hdc_and_sf_flex_regs[7]; static struct gen_perf_query_counter glk_hdc_and_sf_query_counters[38]; static struct gen_perf_query_info glk_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "530d176d-2a18-4014-adf8-1500c6c60835", .counters = glk_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F6100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F416B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F004B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F808000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13920200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss1)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "HDC stalled by L3 (s0.ss0)"; counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_l3_1_mux_regs[77]; static struct gen_perf_query_register_prog glk_l3_1_b_counter_regs[22]; static struct gen_perf_query_register_prog glk_l3_1_flex_regs[7]; static struct gen_perf_query_counter glk_l3_1_query_counters[39]; static struct gen_perf_query_info glk_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "fdee5a5a-f23c-43d1-aa73-f6257c71671d", .counters = glk_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12643400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12653400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C6800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F1554 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A640024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10640000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04640000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C650024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_rasterizer_and_pixel_backend_mux_regs[41]; static struct gen_perf_query_register_prog glk_rasterizer_and_pixel_backend_b_counter_regs[10]; static struct gen_perf_query_register_prog glk_rasterizer_and_pixel_backend_flex_regs[7]; static struct gen_perf_query_counter glk_rasterizer_and_pixel_backend_query_counters[40]; static struct gen_perf_query_info glk_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "6617623e-ca73-4791-b2b7-ddedd0846a0c", .counters = glk_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D7800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D79E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2F0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100E3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0940 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D802F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040E0480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060F0027 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 132; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.slice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_sampler_mux_regs[93]; static struct gen_perf_query_register_prog glk_sampler_b_counter_regs[12]; static struct gen_perf_query_register_prog glk_sampler_flex_regs[7]; static struct gen_perf_query_counter glk_sampler_query_counters[41]; static struct gen_perf_query_info glk_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "f3b2ea63-e82e-4234-b418-44dd20dd34d0", .counters = glk_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141600AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143600AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125300A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145600AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E01A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0065 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F023F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2CC030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04132180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E142000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E150140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C163000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E160068 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A164000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04330043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02330000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0234A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02363460 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08364000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06530043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02530000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E563000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00563400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C564000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9014A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_tdl_1_mux_regs[86]; static struct gen_perf_query_register_prog glk_tdl_1_b_counter_regs[18]; static struct gen_perf_query_register_prog glk_tdl_1_flex_regs[7]; static struct gen_perf_query_counter glk_tdl_1_query_counters[41]; static struct gen_perf_query_info glk_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "14411d35-cbf6-4f5e-b68b-190faf9a1a83", .counters = glk_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E006A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0BC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0302 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C00F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A31E5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150054 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A3280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E350140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18360028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5A3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A3280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_tdl_2_mux_regs[58]; static struct gen_perf_query_register_prog glk_tdl_2_b_counter_regs[6]; static struct gen_perf_query_register_prog glk_tdl_2_flex_regs[7]; static struct gen_perf_query_counter glk_tdl_2_query_counters[41]; static struct gen_perf_query_info glk_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d", .counters = glk_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A026B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0173 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A026B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0069 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F030A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A37E7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A3380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A006F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A352000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A37E7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0254A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 0x2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 92; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } if (perf->sys_vars.subslice_mask & 0x4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 0x1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_compute_extra_mux_regs[37]; static struct gen_perf_query_register_prog glk_compute_extra_b_counter_regs[6]; static struct gen_perf_query_register_prog glk_compute_extra_flex_regs[7]; static struct gen_perf_query_counter glk_compute_extra_query_counters[5]; static struct gen_perf_query_info glk_compute_extra_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extra Gen9", .guid = "15274c82-27d2-4819-876a-7cb1a2c59ba4", .counters = glk_compute_extra_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_compute_extra_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_compute_extra_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = glk_compute_extra_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void glk_register_compute_extra_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_compute_extra_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0094 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F00E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06142000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A3180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A0063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extra__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extra__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extra__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__compute_extra__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__compute_extra__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__compute_extra__fpu1_active_adjusted__read; counter->name = "EU FPU1 Pipe Active including Ext Math"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_test_oa_mux_regs[12]; static struct gen_perf_query_register_prog glk_test_oa_b_counter_regs[22]; static struct gen_perf_query_counter glk_test_oa_query_counters[12]; static struct gen_perf_query_info glk_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "MDAPI testing set Gen9", .guid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf", .counters = glk_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void glk_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800063 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23810008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.166"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog glk_pma__stall_mux_regs[34]; static struct gen_perf_query_register_prog glk_pma__stall_b_counter_regs[9]; static struct gen_perf_query_counter glk_pma__stall_query_counters[4]; static struct gen_perf_query_info glk_pma__stall_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set PMA Stall", .guid = "e6868953-fb47-431d-a060-f785916558fc", .counters = glk_pma__stall_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = glk_pma__stall_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = glk_pma__stall_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void glk_register_pma__stall_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &glk_pma__stall_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C0045 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C2300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C26C4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C264E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x199300AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29904000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00E00021 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0007FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x07000101 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0038FFC7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__pma__stall__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__pma__stall__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = glk__pma__stall__stc_pma_stall__read; counter->name = "STC PMA stall"; counter->desc = "Percentage of time when stencil cache line and an overlapping pixel are causing stalls"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = glk__pma__stall__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = glk__pma__stall__avg_gpu_core_frequency__max(perf); counter->offset = 24; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_glk(struct gen_perf *perf) { glk_register_render_basic_counter_query(perf); glk_register_compute_basic_counter_query(perf); glk_register_render_pipe_profile_counter_query(perf); glk_register_memory_reads_counter_query(perf); glk_register_memory_writes_counter_query(perf); glk_register_compute_extended_counter_query(perf); glk_register_compute_l3_cache_counter_query(perf); glk_register_hdc_and_sf_counter_query(perf); glk_register_l3_1_counter_query(perf); glk_register_rasterizer_and_pixel_backend_counter_query(perf); glk_register_sampler_counter_query(perf); glk_register_tdl_1_counter_query(perf); glk_register_tdl_2_counter_query(perf); glk_register_compute_extra_counter_query(perf); glk_register_test_oa_counter_query(perf); glk_register_pma__stall_counter_query(perf); } static struct gen_perf_query_register_prog cnl_render_basic_mux_regs[98]; static struct gen_perf_query_register_prog cnl_render_basic_b_counter_regs[7]; static struct gen_perf_query_register_prog cnl_render_basic_flex_regs[6]; static struct gen_perf_query_counter cnl_render_basic_query_counters[51]; static struct gen_perf_query_info cnl_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen10", .guid = "2d975e19-7130-41d2-b06f-79d74f91e7c8", .counters = cnl_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18110014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EC0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18910014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0054 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0444 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02738000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04742000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C742000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04752000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C752000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C760800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167702A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A190020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08110061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF62200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F70230 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E994000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A990080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06916000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08916100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E910000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C941100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B086F4F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D080001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F070140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09081E93 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01083160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x030801A6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11080000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F080000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D095000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F095000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03095000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13040154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09044000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D049000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F042000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0507E700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070700D7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47003331 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x390018C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000333 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000407 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D003333 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x410018C6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B001CC6 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x40800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00000202 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FF3F }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00222222 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__sampler00_busy__read; counter->name = "Sampler00 Busy"; counter->desc = "The percentage of time in which Slice0 Sampler0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; } if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__sampler10_busy__read; counter->name = "Sampler10 Busy"; counter->desc = "The percentage of time in which Slice1 Sampler0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; } if (perf->sys_vars.subslice_mask & 9) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gti_vf_throughput__read; counter->name = "GTI Fixed Pipe Throughput"; counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__sampler00_bottleneck__read; counter->name = "Sampler00 Bottleneck"; counter->desc = "The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 228; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gti_depth_throughput__read; counter->name = "GTI Depth Throughput"; counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 260; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__sampler10_bottleneck__read; counter->name = "Sampler10 Bottleneck"; counter->desc = "The percentage of time in which Slice1 Sampler0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; } if (perf->sys_vars.subslice_mask & 9) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 308; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gti_rcc_throughput__read; counter->name = "GTI RCC Throughput"; counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 360; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_compute_basic_mux_regs[129]; static struct gen_perf_query_register_prog cnl_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog cnl_compute_basic_flex_regs[4]; static struct gen_perf_query_counter cnl_compute_basic_query_counters[39]; static struct gen_perf_query_info cnl_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen10", .guid = "eed14f91-5f03-4e3a-8281-ac38030ac573", .counters = cnl_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109A0007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04736000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00734000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02731000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0474A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E748000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06748000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0475A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E758000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06758000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C762800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167797A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0277C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0677C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7B0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E7C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147C0C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0038 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C7D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0019C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A191800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0219C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0619C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A2E52 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1A2880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A2D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A396000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A2900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F40400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F50020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F52000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F52000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF62008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF68000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F7C070 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14FC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EFD2008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A990180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C99000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0499C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0899C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089A2900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9A0051 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029A005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049A005B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AB90600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB90030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA0052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBA2880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A590060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C590003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085A0052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5A2880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F070140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D048000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F042000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0507E700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070700D7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47001011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001330 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D001026 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000081 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B001801 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 9) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; if (perf->sys_vars.subslice_mask & 9) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_render_pipe_profile_mux_regs[123]; static struct gen_perf_query_register_prog cnl_render_pipe_profile_b_counter_regs[5]; static struct gen_perf_query_register_prog cnl_render_pipe_profile_flex_regs[1]; static struct gen_perf_query_counter cnl_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info cnl_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen10", .guid = "0666ccac-f5aa-4dc2-aa12-c6e058f383f3", .counters = cnl_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7003E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A710000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1017001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06700015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00700000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06710800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00710000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C746000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C75A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E754000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E762800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16770330 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A190040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01160031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11177C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11187C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05190000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x110E7800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11130019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F160C80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07162000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x071705C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x011704C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B180015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01185000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07185000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D185000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F185000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03186000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05185000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03190022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F190000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09190000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0E8023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x030E1100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x050E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0F0180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x050F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B100054 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D110006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D114000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05127100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07120073 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21120001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F130002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F144025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11140025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D145200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F158080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0109A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0709A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B092000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D09A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F09A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0309A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0509A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B0B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x030BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x050BC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11044000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13040154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47001111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39001022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F0018A5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D001111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000401 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_memory_reads_mux_regs[56]; static struct gen_perf_query_register_prog cnl_memory_reads_b_counter_regs[26]; static struct gen_perf_query_register_prog cnl_memory_reads_flex_regs[1]; static struct gen_perf_query_counter cnl_memory_reads_query_counters[40]; static struct gen_perf_query_info cnl_memory_reads_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Reads Distribution Gen10", .guid = "3500dcfd-837b-4ec8-b5cf-fe58b966263f", .counters = cnl_memory_reads_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_memory_reads_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_memory_reads_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_memory_reads_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_memory_reads_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_memory_reads_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17066860 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15070017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F072920 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B038000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D038000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F034000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F063180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01063100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0306006B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05060000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11080100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D085000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09046000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F04A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1104A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130401AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B041000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010700E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0707E153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0907E3E2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B07E5E4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D07E7E6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0700EF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000081A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0000082A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000872 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x000008BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0000087A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x000008EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x000008E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x000008F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00000065 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__memory_reads__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_bank0_reads__read; counter->name = "GtiL3Bank0Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_rs_memory_reads__read; counter->name = "GtiRsMemoryReads"; counter->desc = "The total number of GTI memory reads from Resource Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_hiz_memory_reads__read; counter->name = "GtiHizMemoryReads"; counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__memory_reads__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_rcc_memory_reads__read; counter->name = "GtiRccMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_bank1_reads__read; counter->name = "GtiL3Bank1Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__memory_reads__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_cmd_streamer_memory_reads__read; counter->name = "GtiCmdStreamerMemoryReads"; counter->desc = "The total number of GTI memory reads from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_bank2_reads__read; counter->name = "GtiL3Bank2Reads"; counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_memory_reads__read; counter->name = "GtiMemoryReads"; counter->desc = "The total number of GTI memory reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_rcz_memory_reads__read; counter->name = "GtiRczMemoryReads"; counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__memory_reads__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_msc_memory_reads__read; counter->name = "GtiMscMemoryReads"; counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_vf_memory_reads__read; counter->name = "GtiVfMemoryReads"; counter->desc = "The total number of GTI memory reads from Vertex Fetch."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_stc_memory_reads__read; counter->name = "GtiStcMemoryReads"; counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_reads__read; counter->name = "GtiL3Reads"; counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_reads__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_memory_writes_mux_regs[56]; static struct gen_perf_query_register_prog cnl_memory_writes_b_counter_regs[24]; static struct gen_perf_query_register_prog cnl_memory_writes_flex_regs[1]; static struct gen_perf_query_counter cnl_memory_writes_query_counters[40]; static struct gen_perf_query_info cnl_memory_writes_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Memory Writes Distribution Gen10", .guid = "63d18ead-3cfc-4972-a640-5e98b688dfee", .counters = cnl_memory_writes_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_memory_writes_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_memory_writes_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_memory_writes_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_memory_writes_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_memory_writes_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17066860 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15070017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F07000E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B038000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D038000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F034000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F063180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01063100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0306006B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05060000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11080100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D085000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09046000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F04A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1104A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130401AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B041000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010700D0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0707D153 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0907D3D2 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B07D5D4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D07D7D6 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0700DF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000C63 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000081A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000822 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x000008BA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0000087A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x000008EA }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x000008E2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x000008F2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x65432108 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x0000CCCE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x65432108 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x65432108 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002754, .val = 0x000000CA }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__memory_writes__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_memory_writes__read; counter->name = "GtiMemoryWrites"; counter->desc = "The total number of GTI memory writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_ring_accesses__read; counter->name = "GtiRingAccesses"; counter->desc = "The total number of all accesses from GTI to the ring."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_msc_memory_writes__read; counter->name = "GtiMscMemoryWrites"; counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_cmd_streamer_memory_writes__read; counter->name = "GtiCmdStreamerMemoryWrites"; counter->desc = "The total number of GTI memory writes from Command Streamer."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_bank0_writes__read; counter->name = "GtiL3Bank0Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_bank1_writes__read; counter->name = "GtiL3Bank1Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_bank2_writes__read; counter->name = "GtiL3Bank2Writes"; counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_writes__read; counter->name = "GtiL3Writes"; counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__memory_writes__avg_gpu_core_frequency__max(perf); counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_rcc_memory_writes__read; counter->name = "GtiRccMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_so_memory_writes__read; counter->name = "GtiSoMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stream Output."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__memory_writes__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_stc_memory_writes__read; counter->name = "GtiStcMemoryWrites"; counter->desc = "The total number of GTI memory writes from Stencil Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__memory_writes__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_rcz_memory_writes__read; counter->name = "GtiRczMemoryWrites"; counter->desc = "The total number of GTI memory writes from Render Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__gti_hiz_memory_writes__read; counter->name = "GtiHizMemoryWrites"; counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__memory_writes__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_compute_extended_mux_regs[80]; static struct gen_perf_query_register_prog cnl_compute_extended_b_counter_regs[21]; static struct gen_perf_query_register_prog cnl_compute_extended_flex_regs[4]; static struct gen_perf_query_counter cnl_compute_extended_query_counters[38]; static struct gen_perf_query_info cnl_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Extended Gen10", .guid = "1b4d1280-6bbd-4d57-90c6-a03ed6059688", .counters = cnl_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_compute_extended_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { if (perf->sys_vars.subslice_mask & 1) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121B000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161B0009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0474A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A748000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C74A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E74A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12741540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0674A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08742000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0475A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A758000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C75A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E75A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147500AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0675A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08752000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C76A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E76AA0A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x107602AA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E77C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1677FFF0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0277C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0477C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0677C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0877C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00198000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E198000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A195540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C19003A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0219C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0419C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0619C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0819C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1A2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A2980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A2CDA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A0058 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B0900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B0A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B0B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B2317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B0043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10178000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1701FE }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000021 }; } query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000C2A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000C6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000E6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000E7A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000C92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00000CA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000C9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__typed_writes0__read; counter->name = "Typed Writes 0"; counter->desc = "The subslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_typed_atomics0__read; counter->name = "EuTypedAtomics0"; counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__typed_atomics0__read; counter->name = "Typed Atomics 0"; counter->desc = "The subslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_untyped_reads0__read; counter->name = "EuUntypedReads0"; counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__untyped_writes0__read; counter->name = "Untyped Writes 0"; counter->desc = "The subslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 76; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_untyped_atomics0__read; counter->name = "EuUntypedAtomics0"; counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_untyped_writes0__read; counter->name = "EuUntypedWrites0"; counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_a64_untyped_writes0__read; counter->name = "EuA64UntypedWrites0"; counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_typed_writes0__read; counter->name = "EuTypedWrites0"; counter->desc = "The subslice 0 EU Typed Writes subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__typed_reads0__read; counter->name = "Typed Reads 0"; counter->desc = "The subslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__untyped_reads0__read; counter->name = "Untyped Reads 0"; counter->desc = "The subslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_a64_untyped_reads0__read; counter->name = "EuA64UntypedReads0"; counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__eu_typed_reads0__read; counter->name = "EuTypedReads0"; counter->desc = "The subslice 0 EU Typed Reads subslice 0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_extended__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_extended__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_compute_l3_cache_mux_regs[67]; static struct gen_perf_query_register_prog cnl_compute_l3_cache_b_counter_regs[5]; static struct gen_perf_query_register_prog cnl_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter cnl_compute_l3_cache_query_counters[55]; static struct gen_perf_query_info cnl_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen10", .guid = "f3b31b5a-00b3-4fb4-81fd-6446e505534c", .counters = cnl_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EC0080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0052 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C5C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00739000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02739000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167702A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EC5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5251 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EC005C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F3E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F702A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B080360 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F070140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01081060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D080000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09044000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B041000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D048000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F042000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0507E700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070700D7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47001111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39002101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001110 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000429 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B002401 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 24; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank00_accesses__read; counter->name = "Slice0 L3 Bank0 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank01_accesses__read; counter->name = "Slice0 L3 Bank1 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank02_accesses__read; counter->name = "Slice0 L3 Bank2 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank2."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; } if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank10_accesses__read; counter->name = "Slice1 L3 Bank0 Accesses"; counter->desc = "The total number of accesses to Slice1 L3 Bank0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; } if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank11_accesses__read; counter->name = "Slice1 L3 Bank1 Accesses"; counter->desc = "The total number of accesses to Slice1 L3 Bank1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; } if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank12_accesses__read; counter->name = "Slice1 L3 Bank2 Accesses"; counter->desc = "The total number of accesses to Slice1 L3 Bank2."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 308; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 384; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 388; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 392; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_hdc_and_sf_mux_regs[87]; static struct gen_perf_query_register_prog cnl_hdc_and_sf_b_counter_regs[7]; static struct gen_perf_query_register_prog cnl_hdc_and_sf_flex_regs[5]; static struct gen_perf_query_counter cnl_hdc_and_sf_query_counters[42]; static struct gen_perf_query_info cnl_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "890094c5-8615-4f69-a8b9-706c5bcbd713", .counters = cnl_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123A0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BA0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125A0011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00736000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C74A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C75A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E762800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16779570 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B002A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C003E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1901E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A2B50 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A391E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3A2B50 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F41400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F500A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08FBA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02FC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04FC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C99003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9A2B50 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BA2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BA0056 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A596000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C590003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5A2B50 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130E03C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01181000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010E0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x110E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01118000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B142000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01092000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09041000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000408 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000084 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000300 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFE }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "Slice0 Subslice1 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "Slice0 Subslice2 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read; counter->name = "Slice1 Subslice0 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Subslice0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read; counter->name = "Slice1 Subslice1 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Subslice1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "Slice0 Subslice0 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_l3_1_mux_regs[81]; static struct gen_perf_query_register_prog cnl_l3_1_b_counter_regs[11]; static struct gen_perf_query_register_prog cnl_l3_1_flex_regs[5]; static struct gen_perf_query_counter cnl_l3_1_query_counters[42]; static struct gen_perf_query_info cnl_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "e56f7dd7-ff55-4bae-89a1-a526a2e3b0d6", .counters = cnl_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1661001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1665001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1669001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C001D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02610024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E610000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02652400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E650000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04690024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C2820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C3832 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C05A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C1010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0073F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02738000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473D000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673D000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16778A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04784000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7B0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EC0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CEC0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EC3600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F31000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F32000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F70800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D001100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B0000C7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x20000801 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0111FEEE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x40001001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0222FDDD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x80002002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0444FBBB }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__l31_bank2_stalled__read; counter->name = "Slice1 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_l3_2_mux_regs[87]; static struct gen_perf_query_register_prog cnl_l3_2_b_counter_regs[11]; static struct gen_perf_query_register_prog cnl_l3_2_flex_regs[5]; static struct gen_perf_query_counter cnl_l3_2_query_counters[42]; static struct gen_perf_query_info cnl_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_2", .guid = "918834e2-a1a4-4d77-9f3a-0c229f8d803f", .counters = cnl_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E1001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E5001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E9001A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC1C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12EC0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC001D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C3600 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0A88 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0504 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0073F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02739000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473D000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673D000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16778A80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02E10024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E10000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE10000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02E52400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04E90024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EC0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EC2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC2820 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEC3832 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0580 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18ED8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEE1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F3D000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F38000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F3C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F3C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F78280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F78000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F84000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000883 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D001064 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000C60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000C04 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x20000801 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0111FEEE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x40001001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0222FDDD }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x80002002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0444FBBB }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__l31_bank1_stalled__read; counter->name = "Slice1 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__l31_bank0_stalled__read; counter->name = "Slice1 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice1 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__l30_bank2_stalled__read; counter->name = "Slice0 L3 Bank2 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__l31_bank2_active__read; counter->name = "Slice1 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice1 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__l31_bank1_active__read; counter->name = "Slice1 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice1 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__l3_2__l31_bank0_active__read; counter->name = "Slice1 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice1 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__l3_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_rasterizer_and_pixel_backend_mux_regs[93]; static struct gen_perf_query_register_prog cnl_rasterizer_and_pixel_backend_b_counter_regs[13]; static struct gen_perf_query_register_prog cnl_rasterizer_and_pixel_backend_flex_regs[5]; static struct gen_perf_query_counter cnl_rasterizer_and_pixel_backend_query_counters[46]; static struct gen_perf_query_info cnl_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "2e95713a-c6d8-47a9-9207-eba3e208be51", .counters = cnl_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C710004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10747000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12756800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04795000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x127C01C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF10004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F47000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F56800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F95000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12FC01C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C4044 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00710010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02738000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04732000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00736000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08740037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C740000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A750F36 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10750000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04751000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C752000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E750000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C760800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E768800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167767E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C790017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08790000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0088 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E7C0032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x107C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F10200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F10000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F40DC0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F50D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F5003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF54000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F50000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF62200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF6A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F71030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF905C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0220 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EFC1900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10FC0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000402 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000101 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000801 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFFE }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFD }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer1_input_available__read; counter->name = "Slice1 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice1 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_values0_ready__read; counter->name = "Slice0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_data0_ready__read; counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_values1_ready__read; counter->name = "Slice1 Pixel Values Ready"; counter->desc = "The percentage of time in which slice1 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_output1_available__read; counter->name = "Slice1 PS Output Available"; counter->desc = "The percentage of time in which slice1 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; if (perf->sys_vars.slice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer1_output_ready__read; counter->name = "Slice1 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice1 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_data1_ready__read; counter->name = "Slice1 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_output0_available__read; counter->name = "Slice0 PS Output Available"; counter->desc = "The percentage of time in which slice0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 288; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_sampler_mux_regs[144]; static struct gen_perf_query_register_prog cnl_sampler_b_counter_regs[15]; static struct gen_perf_query_register_prog cnl_sampler_flex_regs[5]; static struct gen_perf_query_counter cnl_sampler_query_counters[46]; static struct gen_perf_query_info cnl_sampler_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler", .guid = "9bcf4ff2-c15f-4bea-8ec8-8db87791942e", .counters = cnl_sampler_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_sampler_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_sampler_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_sampler_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_sampler_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_sampler_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14141400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1614000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14161400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14341400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1634000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14361400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14941400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1694000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14961400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B41400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B4000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B61400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14541400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1654000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14561400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0073C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04742000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A74A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04752000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A75A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C760800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E77C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1677A950 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C77C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7BA828 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147CE800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x087CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C7D8200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00140050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06145800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10140000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18140000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A150001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06160043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3900A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08345850 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10340000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C340020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08358000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04362180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A360000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F40140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F5000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF60002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F77C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08FB8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04FC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EFD2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A992000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C990001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06994000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C945850 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E940000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C940002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08952000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02962180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06960000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB90014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB45850 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EB40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AB48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B51000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B60043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B60000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B60000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A590A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08594000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A545850 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10540000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E540000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08554000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04560043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08560000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000143 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001110 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000C61 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F0018C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000842 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000480 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000018 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000600 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00001800 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FCFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler10_input_available__read; counter->name = "Slice1 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice1 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__sampler__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler11_input_available__read; counter->name = "Slice1 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice1 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler10_output_ready__read; counter->name = "Slice1 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 252; } if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__sampler__sampler11_output_ready__read; counter->name = "Slice1 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice1 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__sampler__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_tdl_1_mux_regs[143]; static struct gen_perf_query_register_prog cnl_tdl_1_b_counter_regs[15]; static struct gen_perf_query_register_prog cnl_tdl_1_flex_regs[5]; static struct gen_perf_query_counter cnl_tdl_1_query_counters[46]; static struct gen_perf_query_info cnl_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "c46c7bb5-f26d-4634-b491-902394af85b1", .counters = cnl_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12580000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02733000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0474A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A748000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0475A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A758000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C762800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E77C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1677A950 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0277C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7BA802 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x087B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147CE800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x047C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x067CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C7D8008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02194000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A142000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0015C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A150002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02168000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0018A1A3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0618A500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3900A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04394000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C342800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A348000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A35000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08351000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A360140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04368000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0838A5A3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023800A1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F40140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F5000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F52000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF60008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F77C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EFD2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD0200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A992000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C990001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08994000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E940028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C940008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9500C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08954000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A964000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C960002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C98A5A3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049800A1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB90014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EB40280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB40020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB50300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB60028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB68000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB8A5A3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B8A100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A590A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06594000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C548002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E540002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A550030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08552000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A561400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58A5A3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258A100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D00042B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F001081 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FCFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_thread11_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread02_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread10_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread00_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_thread10_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice0"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 252; } if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread11_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread01_ready_for_dispatch__read; counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 320; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_tdl_2_mux_regs[110]; static struct gen_perf_query_register_prog cnl_tdl_2_b_counter_regs[5]; static struct gen_perf_query_register_prog cnl_tdl_2_flex_regs[5]; static struct gen_perf_query_counter cnl_tdl_2_query_counters[46]; static struct gen_perf_query_info cnl_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "aa2d6ab4-99b3-42f8-94d6-4a9aa2baedaf", .counters = cnl_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = cnl_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void cnl_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12184D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12384D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12984D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B84D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12584D60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C2A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00738000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02737000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12740140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1475000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16777C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04774000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C778000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x087BA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x027CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x047CC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D2800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C190001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E140028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1500C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A164000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C160002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C18AFA7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C390014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E340280 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A350300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C360028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38AFA7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F48000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F42000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F52000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF6000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F7C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF74000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB00A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD0A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06994000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08994000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C94000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08956000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08968000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0298A700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049800AF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB94000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB400A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B58000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB50001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB68000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB68000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B8A700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B800AF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02594000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04594000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A54A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00558000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08551000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0058A700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025800AF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21003000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27000071 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D00C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B003000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F002C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D001111 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000421 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39001080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header11_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; } if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header11_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice1 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header10_ready_port1__read; counter->name = "Thread Header Ready on Slice1 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 220; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header10_ready_port0__read; counter->name = "Thread Header Ready on Slice1 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 284; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = cnl__tdl_2__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog cnl_test_oa_mux_regs[26]; static struct gen_perf_query_register_prog cnl_test_oa_b_counter_regs[21]; static struct gen_perf_query_counter cnl_test_oa_query_counters[12]; static struct gen_perf_query_info cnl_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TestOa", .guid = "db41edd4-d8e7-4730-ad11-b9a2d6833503", .counters = cnl_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = cnl_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = cnl_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void cnl_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &cnl_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17060000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13034000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07060066 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05060000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F080040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F041000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.6666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = cnl__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.3333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.3333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.16666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = cnl__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_cnl(struct gen_perf *perf) { cnl_register_render_basic_counter_query(perf); cnl_register_compute_basic_counter_query(perf); cnl_register_render_pipe_profile_counter_query(perf); cnl_register_memory_reads_counter_query(perf); cnl_register_memory_writes_counter_query(perf); cnl_register_compute_extended_counter_query(perf); cnl_register_compute_l3_cache_counter_query(perf); cnl_register_hdc_and_sf_counter_query(perf); cnl_register_l3_1_counter_query(perf); cnl_register_l3_2_counter_query(perf); cnl_register_rasterizer_and_pixel_backend_counter_query(perf); cnl_register_sampler_counter_query(perf); cnl_register_tdl_1_counter_query(perf); cnl_register_tdl_2_counter_query(perf); cnl_register_test_oa_counter_query(perf); } static struct gen_perf_query_register_prog icl_render_basic_mux_regs[61]; static struct gen_perf_query_register_prog icl_render_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_render_basic_flex_regs[6]; static struct gen_perf_query_counter icl_render_basic_query_counters[41]; static struct gen_perf_query_info icl_render_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics Basic Gen11", .guid = "621e248e-29c3-404d-a1b1-bb69610c4a99", .counters = icl_render_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_render_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_render_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_render_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_render_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_render_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142C0014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14120700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121500E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C200014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16212800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C2041 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E040005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24061800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04120023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02150980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1815000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E18A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14190028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C01C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C01C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C9400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C00A7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081D8100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D0004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085C9497 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CA700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5D000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E1EEF80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F2404 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F0092 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0303 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0303 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F4001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0xFFFFFFFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00000052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__sampler_l1_misses__read; counter->name = "Sampler Cache Misses"; counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__sampler00_busy__read; counter->name = "Sampler00 Busy"; counter->desc = "The percentage of time in which Slice0 Sampler0 has been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } if (perf->sys_vars.subslice_mask & 9) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__samplers_busy__read; counter->name = "Samplers Busy"; counter->desc = "The percentage of time in which samplers have been processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 68; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__render_basic__avg_gpu_core_frequency__max(perf); counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__sampler00_bottleneck__read; counter->name = "Sampler00 Bottleneck"; counter->desc = "The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; if (perf->sys_vars.subslice_mask & 9) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_basic__sampler_bottleneck__read; counter->name = "Samplers Bottleneck"; counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_compute_basic_mux_regs[114]; static struct gen_perf_query_register_prog icl_compute_basic_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_compute_basic_flex_regs[4]; static struct gen_perf_query_counter icl_compute_basic_query_counters[40]; static struct gen_perf_query_info icl_compute_basic_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics Basic Gen11", .guid = "233a477b-f8f0-40f4-bf57-01440c3701d9", .counters = icl_compute_basic_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_compute_basic_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_compute_basic_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_compute_basic_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_compute_basic_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_compute_basic_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12230012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10230019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12A30012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10A30019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A200400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C200020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A230031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E231E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0223003D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04230032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06230033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00230000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AA01000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CA00008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02A08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06A08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AA08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AA31880 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EA3003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00A31E80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02A31900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04A31980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E044055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040141 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600CC }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24067E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18123000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A12000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0212C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0612C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A12C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A134000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06132000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150380 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1815000D }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0415C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14190020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141D0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C01C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C01C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0097 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C9400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1CA700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081D8100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085C9497 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C00A7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5D0013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E1E0F80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x201E000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F2524 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F2522 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2430 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0303 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F3003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00000008 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__untyped_bytes_read__read; counter->name = "Untyped Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__typed_bytes_written__read; counter->name = "Typed Bytes Written"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__typed_atomics__read; counter->name = "Typed Atomics Accesses"; counter->desc = "The total number of typed atomic accesses via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__compute_basic__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__untyped_bytes_written__read; counter->name = "Untyped Writes"; counter->desc = "The total number of untyped memory bytes written via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__typed_bytes_read__read; counter->name = "Typed Bytes Read"; counter->desc = "The total number of typed memory bytes read via Data Port."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_basic__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_basic__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_compute_extended_mux_regs[95]; static struct gen_perf_query_register_prog icl_compute_extended_b_counter_regs[24]; static struct gen_perf_query_counter icl_compute_extended_query_counters[22]; static struct gen_perf_query_info icl_compute_extended_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "ComputeExtended Gen11", .guid = "43eb7fc1-dc5e-45e2-a90a-0053f5397271", .counters = icl_compute_extended_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_compute_extended_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_compute_extended_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void icl_register_compute_extended_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_compute_extended_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1222000B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16220009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12230019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10230012 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1EF800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1E0007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FF800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A202AA0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C200005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C208000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00214000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E214000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14214000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16210555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00220011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06220900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08220A13 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A220B15 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C222317 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E220043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02231AB4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04231DBA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06230039 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00230000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C044400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2406FD00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2606007F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0015C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16157FF8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0415C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0618A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0818A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A18A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C18A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0218A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0418A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E19A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12195540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1419000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A19A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C19A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16136860 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24000004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20000040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00132D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2413 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F3013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x30000036 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x01FFFE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x31000034 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x01FFFE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C9A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000C92 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000CA2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000E42 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00000E6A }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000C32 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x87643210 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00001811 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002748, .val = 0x87654310 }; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__untyped_writes_per_cache_line__read; counter->name = "UntypedWritesPerCacheLine"; counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 0; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__eu_typed_atomics00__read; counter->name = "Eu Typed Atomics 00"; counter->desc = "Slice0 Dualsubslice 0 Eu Typed Atomics"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__typed_atomics00__read; counter->name = "Typed Atomics 00"; counter->desc = "Slice 0 Dualsubslice 0 typed atomics."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__typed_atomics_per_cache_line__read; counter->name = "TypedAtomicsPerCacheLine"; counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 24; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__eu_a64_untyped_reads00__read; counter->name = "Eu 64 Untyped Reads 00"; counter->desc = "Slice0 Dualsubslice 0 Eu 64 Untyped Reads"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 28; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__eu_a32_untyped_writes00__read; counter->name = "Eu A32 Untyped Writes 00"; counter->desc = "Slice0 Dualsubslice 0 Eu A32 Untyped Writes"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__compute_extended__avg_gpu_core_frequency__max(perf); counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__eu_typed_reads00__read; counter->name = "Eu Typed Reads 00"; counter->desc = "Slice0 Dualsubslice 0 Eu Typed Reads"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__eu_typed_writes00__read; counter->name = "Eu Typed Writes 00"; counter->desc = "Slice0 Dualsubslice 0 Eu Typed Writes"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__typed_writes00__read; counter->name = "Typed Writes 00"; counter->desc = "Slice 0 Dualsubslice 0 typed writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__typed_writes_per_cache_line__read; counter->name = "TypedWritesPerCacheLine"; counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 96; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__untyped_writes00__read; counter->name = "Untyped Writes 00"; counter->desc = "Slice 0 Dualsubslice 0 untyped writes (including SLM writes)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__untyped_reads00__read; counter->name = "Untyped Reads 00"; counter->desc = "Slice 0 Dualsubslice 0 untyped reads (including SLM reads)."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__eu_a64_untyped_writes00__read; counter->name = "Eu A64 Untyped Writes 00"; counter->desc = "Slice0 Dualsubslice 0 Eu A64 Untyped Writes"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__untyped_reads_per_cache_line__read; counter->name = "UntypedReadsPerCacheLine"; counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__typed_reads00__read; counter->name = "Typed Reads 00"; counter->desc = "Slice 0 Dualsubslice 0 typed reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_extended__typed_reads_per_cache_line__read; counter->name = "TypedReadsPerCacheLine"; counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 0 /* undefined */; counter->offset = 144; } if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_extended__eu_a32_untyped_reads00__read; counter->name = "Eu A32 Untyped Reads 00"; counter->desc = "Slice0 Dualsubslice 0 Eu A32 Untyped Reads"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_compute_l3_cache_mux_regs[62]; static struct gen_perf_query_register_prog icl_compute_l3_cache_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_compute_l3_cache_flex_regs[7]; static struct gen_perf_query_counter icl_compute_l3_cache_query_counters[57]; static struct gen_perf_query_info icl_compute_l3_cache_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Compute Metrics L3 Cache Gen11", .guid = "022b8913-ae9f-4559-abcd-583e586170d0", .counters = icl_compute_l3_cache_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_compute_l3_cache_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_compute_l3_cache_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_compute_l3_cache_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_compute_l3_cache_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_compute_l3_cache_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14120700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121500E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040154 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E040055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24067E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C120023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E12152B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00121480 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02120028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04120000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A13D000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04136000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C150980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154D80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154C9A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06150018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A150000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1473A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1217241C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22000550 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18137C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A130001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061434A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00140000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081710B0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F1124 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4849 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F3100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F3131 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0031 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank03_accesses__read; counter->name = "Slice0 L3 Bank3 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank00_accesses__read; counter->name = "Slice0 L3 Bank0 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank0."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank01_accesses__read; counter->name = "Slice0 L3 Bank1 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank02_accesses__read; counter->name = "Slice0 L3 Bank2 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank2."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank04_accesses__read; counter->name = "Slice0 L3 Bank4 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank4."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank05_accesses__read; counter->name = "Slice0 L3 Bank5 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank5."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank06_accesses__read; counter->name = "Slice0 L3 Bank6 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank6."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_bank07_accesses__read; counter->name = "Slice0 L3 Bank7 Accesses"; counter->desc = "The total number of accesses to Slice0 L3 Bank7."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_accesses__read; counter->name = "L3 Accesses"; counter->desc = "The total number of L3 accesses from all entities."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_sampler_throughput__read; counter->name = "L3 Sampler Throughput"; counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_avg_ipc_rate__read; counter->name = "EU AVG IPC Rate"; counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 2.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_binary_fpu0_instruction__read; counter->name = "EU FPU0 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_hybrid_fpu0_instruction__read; counter->name = "EU FPU0 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__fpu1_active__read; counter->name = "EU FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__fpu0_active__read; counter->name = "EU FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_misses__read; counter->name = "L3 Misses"; counter->desc = "The total number of L3 misses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_move_fpu0_instruction__read; counter->name = "EU FPU0 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__sampler_accesses__read; counter->name = "Sampler Accesses"; counter->desc = "The total number of messages send to samplers."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_hybrid_fpu1_instruction__read; counter->name = "EU FPU1 Hybrid Instruction"; counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__compute_l3_cache__avg_gpu_core_frequency__max(perf); counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_lookups__read; counter->name = "L3 Lookup Accesses w/o IC"; counter->desc = "The total number of L3 cache lookup accesses w/o IC."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__gti_read_throughput__read; counter->name = "GTI Read Throughput"; counter->desc = "The total number of GPU memory bytes read from GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_ternary_fpu0_instruction__read; counter->name = "EU FPU0 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 276; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__gti_l3_throughput__read; counter->name = "GTI L3 Throughput"; counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 296; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 304; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_move_fpu1_instruction__read; counter->name = "EU FPU1 Move Instruction"; counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 324; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 344; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 352; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_total_throughput__read; counter->name = "L3 Total Throughput"; counter->desc = "The total number of GPU memory bytes transferred via L3."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 360; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__gti_write_throughput__read; counter->name = "GTI Write Throughput"; counter->desc = "The total number of GPU memory bytes written to GTI."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 368; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 376; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 384; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__compute_l3_cache__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 392; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_binary_fpu1_instruction__read; counter->name = "EU FPU1 Binary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 400; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_ternary_fpu1_instruction__read; counter->name = "EU FPU1 Ternary Instruction"; counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 404; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__compute_l3_cache__eu_send_active__read; counter->name = "EU Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 408; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_render_pipe_profile_mux_regs[101]; static struct gen_perf_query_register_prog icl_render_pipe_profile_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_render_pipe_profile_flex_regs[1]; static struct gen_perf_query_counter icl_render_pipe_profile_query_counters[43]; static struct gen_perf_query_info icl_render_pipe_profile_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Render Metrics for 3D Pipeline Profile Gen11", .guid = "03c7a167-2abc-4ba6-878a-f1d80082abca", .counters = icl_render_pipe_profile_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_render_pipe_profile_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_render_pipe_profile_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_render_pipe_profile_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_render_pipe_profile_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_render_pipe_profile_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F001E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1017001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1F0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A200800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x26060038 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16157E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C160022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08160000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C170540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04170000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C181000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12195000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14190001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100B7C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10107C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16100000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120703C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10090000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06010080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E014180 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00014000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060B0015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0B2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020BA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040BA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0E0A02 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0EA800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F0800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A100017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04107113 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18100020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08100000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08110C40 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02110C80 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00024000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06028000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E02C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00039000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06036000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0803A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A032000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E035000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0203A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0403A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00044000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E044000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C068000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00070032 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E070033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04070000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08098011 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00090980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18090A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02090000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04098000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06098000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A098000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C098000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F36DB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F491B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F001B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F1B41 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F2100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F4141 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F1160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F2120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F0141 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F1160 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3111 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__vs_bottleneck__read; counter->name = "VS Bottleneck"; counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__hi_depth_bottleneck__read; counter->name = "Hi-Depth Bottleneck"; counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__gs_bottleneck__read; counter->name = "GS Bottleneck"; counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__bc_bottleneck__read; counter->name = "BC Bottleneck"; counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__hs_stall__read; counter->name = "HS Stall"; counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 60; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__render_pipe_profile__avg_gpu_core_frequency__max(perf); counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__vf_bottleneck__read; counter->name = "VF Bottleneck"; counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__sf_bottleneck__read; counter->name = "Strip-Fans Bottleneck"; counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__sf_stall__read; counter->name = "SF Stall"; counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 140; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__hs_bottleneck__read; counter->name = "HS Bottleneck"; counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__cl_stall__read; counter->name = "CL Stall"; counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__so_bottleneck__read; counter->name = "SO Bottleneck"; counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__ds_bottleneck__read; counter->name = "DS Bottleneck"; counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__cl_bottleneck__read; counter->name = "Clipper Bottleneck"; counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__ds_stall__read; counter->name = "DS Stall"; counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__early_depth_bottleneck__read; counter->name = "Early Depth Bottleneck"; counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__render_pipe_profile__so_stall__read; counter->name = "SO Stall"; counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__render_pipe_profile__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_hdc_and_sf_mux_regs[79]; static struct gen_perf_query_register_prog icl_hdc_and_sf_b_counter_regs[7]; static struct gen_perf_query_register_prog icl_hdc_and_sf_flex_regs[5]; static struct gen_perf_query_counter icl_hdc_and_sf_query_counters[41]; static struct gen_perf_query_info icl_hdc_and_sf_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set HDCAndSF", .guid = "c5cbc488-6569-41dd-9128-42bf6f0d317c", .counters = icl_hdc_and_sf_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_hdc_and_sf_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_hdc_and_sf_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_hdc_and_sf_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_hdc_and_sf_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_hdc_and_sf_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1223000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10230009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1263000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12A3000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10A30009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12E3000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E30009 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150019 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C20000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C231900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E23003C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00230000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C600020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02608000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E631900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00631E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04A08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06A08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02A31E32 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00A30000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08E08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE08000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04E31E32 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00E30000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E040015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050054 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24063F00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14090040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A120020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0412C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0612C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0214C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00150047 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16156000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1419000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1F3061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F3030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3330 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFE }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__poly_data_ready__read; counter->name = "Polygon Data Ready"; counter->desc = "The percentage of time in which geometry pipeline output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__hdc_and_sf__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; counter->name = "Slice0 Dualsubslice1 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice1)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; counter->name = "Slice0 Dualsubslice2 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice2)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; counter->name = "Slice0 Dualsubslice0 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice0)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__hdc_and_sf__non_sampler_shader03_access_stalled_on_l3__read; counter->name = "Slice0 Dualsubslice3 Non-sampler Shader Access Stalled On L3"; counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Dualsubslice3)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__hdc_and_sf__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_rasterizer_and_pixel_backend_mux_regs[84]; static struct gen_perf_query_register_prog icl_rasterizer_and_pixel_backend_b_counter_regs[11]; static struct gen_perf_query_register_prog icl_rasterizer_and_pixel_backend_flex_regs[5]; static struct gen_perf_query_counter icl_rasterizer_and_pixel_backend_query_counters[44]; static struct gen_perf_query_info icl_rasterizer_and_pixel_backend_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set RasterizerAndPixelBackend", .guid = "0316ce4f-e03f-4738-8262-13528fce8eea", .counters = icl_rasterizer_and_pixel_backend_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_rasterizer_and_pixel_backend_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_rasterizer_and_pixel_backend_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_rasterizer_and_pixel_backend_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_rasterizer_and_pixel_backend_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_rasterizer_and_pixel_backend_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140A001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040C5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140F001F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04115017 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10136000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1213001C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16140000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0018 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045545 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2406DF00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x26060007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00084000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02084000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000A3080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x160A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020C05C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080C0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x160F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08110000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18120C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613092F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08134025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148066 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10140000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0614C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161500E8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08161000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08184000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1A0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121D0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1F0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4904 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F5050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F1040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F4010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F5033 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000038 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFEF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__ps_output00_available__read; counter->name = "Slice0 Pipe0 PS Output Available"; counter->desc = "The percentage of time in which slice0 pipe0 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__ps_output01_available__read; counter->name = "Slice0 Pipe1 PS Output Available"; counter->desc = "The percentage of time in which slice0 pipe1 PS output is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__pixel_values01_ready__read; counter->name = "Slice0 Pipe1 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pipe1 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__pixel_data00_ready__read; counter->name = "Slice0 Pipe0 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__pixel_data01_ready__read; counter->name = "Slice0 Pipe1 Post-EarlyZ Pixel Data Ready"; counter->desc = "The percentage of time in which slice0 pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__rasterizer0_input_available__read; counter->name = "Slice0 Rasterizer Input Available"; counter->desc = "The percentage of time in which slice0 rasterizer input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__pixel_values00_ready__read; counter->name = "Slice0 Pipe0 Pixel Values Ready"; counter->desc = "The percentage of time in which slice0 pipe0 pixel values are ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; counter->name = "Slice0 Rasterizer Output Ready"; counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 220; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__rasterizer_and_pixel_backend__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_l3_1_mux_regs[69]; static struct gen_perf_query_register_prog icl_l3_1_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_l3_1_flex_regs[5]; static struct gen_perf_query_counter icl_l3_1_query_counters[44]; static struct gen_perf_query_info icl_l3_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set L3_1", .guid = "21d69ec3-91e1-48a8-acd6-c0c4ec6e819a", .counters = icl_l3_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_l3_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_l3_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_l3_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_l3_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_l3_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17340000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17740000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17B40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17F40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16340000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16740000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07340037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21340000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09740037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21740000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BB40037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21B40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0DF40037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21F40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0000A7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08012000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A034000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C038000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C340037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20340000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E740037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20740000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B40037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20B40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F40037 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20F40000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E040055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050070 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04058000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06056000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24067E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02074000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04078000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06137000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2A1F0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2460 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F0124 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0133 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F6060 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F0000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank1_active__read; counter->name = "Slice0 L3 Bank1 Active"; counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank5_active__read; counter->name = "Slice0 L3 Bank5 Active"; counter->desc = "The percentage of time in which slice0 L3 bank5 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__l3_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank3_active__read; counter->name = "Slice0 L3 Bank3 Active"; counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 148; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank6_active__read; counter->name = "Slice0 L3 Bank6 Active"; counter->desc = "The percentage of time in which slice0 L3 bank6 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank2_active__read; counter->name = "Slice0 L3 Bank2 Active"; counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank0_active__read; counter->name = "Slice0 L3 Bank0 Active"; counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank7_active__read; counter->name = "Slice0 L3 Bank7 Active"; counter->desc = "The percentage of time in which slice0 L3 bank7 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; } if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_1__l30_bank4_active__read; counter->name = "Slice0 L3 Bank4 Active"; counter->desc = "The percentage of time in which slice0 L3 bank4 is active"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_l3_2_mux_regs[27]; static struct gen_perf_query_register_prog icl_l3_2_b_counter_regs[13]; static struct gen_perf_query_register_prog icl_l3_2_flex_regs[6]; static struct gen_perf_query_counter icl_l3_2_query_counters[29]; static struct gen_perf_query_info icl_l3_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gen11 L2Bank0 stalled metric set", .guid = "e60e9155-6830-4aec-baf2-1c3c15a73869", .counters = icl_l3_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_l3_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_l3_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_l3_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_l3_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_l3_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10050C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12050002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00050025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06050900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080508EA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0508AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C050A21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E050A60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24068100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F0000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000022 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FCFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00000053 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__l3_2__avg_gpu_core_frequency__max(perf); counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__l30_bank0_stalled__read; counter->name = "Slice0 L3 Bank0 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 124; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_2__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_l3_3_mux_regs[27]; static struct gen_perf_query_register_prog icl_l3_3_b_counter_regs[13]; static struct gen_perf_query_register_prog icl_l3_3_flex_regs[6]; static struct gen_perf_query_counter icl_l3_3_query_counters[29]; static struct gen_perf_query_info icl_l3_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gen11 L2Bank1 stalled metric set", .guid = "47c364d5-1799-4d17-9447-add9358c6451", .counters = icl_l3_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_l3_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_l3_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_l3_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_l3_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_l3_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10050400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00050025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06050900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080508EA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0508AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C050A21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E050A60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24068100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F0000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000022 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FCFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00000053 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__l30_bank1_stalled__read; counter->name = "Slice0 L3 Bank1 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__l3_3__avg_gpu_core_frequency__max(perf); counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 108; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 124; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_3__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_l3_4_mux_regs[56]; static struct gen_perf_query_register_prog icl_l3_4_b_counter_regs[13]; static struct gen_perf_query_register_prog icl_l3_4_flex_regs[6]; static struct gen_perf_query_counter icl_l3_4_query_counters[29]; static struct gen_perf_query_info icl_l3_4_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gen11 L2Bank4 stalled metric set", .guid = "e5ab5c08-3130-4469-8eaf-b23d3dc817d4", .counters = icl_l3_4_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_l3_4_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_l3_4_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_l3_4_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_l3_4_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_l3_4_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10010C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12010002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E005500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10000155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00010025 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06010900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080108EA }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0108AB }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C010A21 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E010A60 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C040400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24068100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18125540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A120015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A13F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0814C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16152AA8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F0000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000022 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FCFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00000053 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__l3_4__avg_gpu_core_frequency__max(perf); counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__l30_bank4_stalled__read; counter->name = "Slice0 L3 Bank4 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank4 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_4__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_4__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_l3_5_mux_regs[56]; static struct gen_perf_query_register_prog icl_l3_5_b_counter_regs[13]; static struct gen_perf_query_register_prog icl_l3_5_flex_regs[6]; static struct gen_perf_query_counter icl_l3_5_query_counters[29]; static struct gen_perf_query_info icl_l3_5_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gen11 L2Bank5 stalled metric set", .guid = "6cdf23c1-f725-414c-959a-c90fa5571b1f", .counters = icl_l3_5_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_l3_5_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_l3_5_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_l3_5_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_l3_5_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_l3_5_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10010400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C000400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E005500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10000155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00010022 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06010840 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08010828 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A010969 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C010AA4 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E010AE3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14010000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C040400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24068100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E124000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18125540 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A120015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A13F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0814C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16152AA8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F0000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000022 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF8 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000402 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF1F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00001002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FCFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00011010 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00050012 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00052051 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00000053 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__l3_5__avg_gpu_core_frequency__max(perf); counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 100; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 116; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__l3_5__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; if (perf->sys_vars.slice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__l30_bank5_stalled__read; counter->name = "Slice0 L3 Bank5 Stalled"; counter->desc = "The percentage of time in which slice0 L3 bank5 is stalled"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__l3_5__eu_thread_occupancy__read; counter->name = "EU Thread Occupancy"; counter->desc = "The percentage of time in which hardware threads occupied EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_sampler_1_mux_regs[168]; static struct gen_perf_query_register_prog icl_sampler_1_b_counter_regs[21]; static struct gen_perf_query_register_prog icl_sampler_1_flex_regs[5]; static struct gen_perf_query_counter icl_sampler_1_query_counters[43]; static struct gen_perf_query_info icl_sampler_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler 1", .guid = "51a2eb6d-9fad-4489-8f22-ab845fe7882a", .counters = icl_sampler_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_sampler_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_sampler_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_sampler_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_sampler_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_sampler_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142A0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142F0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146A0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146F0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14AA0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14AF0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EA0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EF0165 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042A1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062AC038 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0048 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5F000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C600014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16612800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006A1800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026A0038 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6A00F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046A0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6F2440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A9EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9E0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AA02A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CA00001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16A102A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CAA1C30 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10AA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AAF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AAA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18ACAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AAF2440 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10AF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DE8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADE3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDF3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00E04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AE000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E10002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EA1C30 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EA0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EF0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EF2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EF0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2406FF00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E08A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02082000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14090050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1812FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A12002B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A13F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04136000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16152AD0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0418A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A198000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C19A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121D5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141D0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F4030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F1010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F4040 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000018 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000600 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00001800 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FCFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00018000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00060000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00003FFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler02_input_available__read; counter->name = "Slice0 Subslice2 Input Available"; counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler00_input_available__read; counter->name = "Slice0 Subslice0 Input Available"; counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 28; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler01_input_available__read; counter->name = "Slice0 Subslice1 Input Available"; counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; if (perf->sys_vars.subslice_mask & 64) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler06_input_available__read; counter->name = "Slice0 Subslice6 Input Available"; counter->desc = "The percentage of time in which slice0 subslice6 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 104; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__sampler_1__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 144; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler04_input_available__read; counter->name = "Slice0 Subslice4 Input Available"; counter->desc = "The percentage of time in which slice0 subslice4 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 156; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler03_input_available__read; counter->name = "Slice0 Subslice3 Input Available"; counter->desc = "The percentage of time in which slice0 subslice3 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; if (perf->sys_vars.subslice_mask & 32) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler05_input_available__read; counter->name = "Slice0 Subslice5 Input Available"; counter->desc = "The percentage of time in which slice0 subslice5 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 212; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; if (perf->sys_vars.subslice_mask & 128) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_1__sampler07_input_available__read; counter->name = "Slice0 Subslice7 Input Available"; counter->desc = "The percentage of time in which slice0 subslice7 sampler input is available"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_sampler_2_mux_regs[137]; static struct gen_perf_query_register_prog icl_sampler_2_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_sampler_2_flex_regs[5]; static struct gen_perf_query_counter icl_sampler_2_query_counters[44]; static struct gen_perf_query_info icl_sampler_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set Sampler 2", .guid = "afc0f021-8c33-4d60-803d-93487f96c7c1", .counters = icl_sampler_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_sampler_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_sampler_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_sampler_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_sampler_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_sampler_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142D0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14320005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146D0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14720005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14AD0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B20005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14ED0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F20005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C200014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16212800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22290010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2A00D0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D0033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E300080 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A310008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E321980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02320000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12698000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006D1980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026D0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A702000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08718000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02720033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x189E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06A04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08A04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06A18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08A18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16A98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08AAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AAC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CAC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD1980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AF4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB00002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B20033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DE8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADE0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDF0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE98000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CEAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04ED1980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02ED0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EF4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CF00020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F10002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F20033 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F20000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E040055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A051000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600C0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24067E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02082000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0612C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0812C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0214C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1815000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E18A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14190028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2A1F0061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2430 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F0124 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F5047 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3050 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler02_output_ready__read; counter->name = "Slice0 Subslice2 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.subslice_mask & 64) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler06_output_ready__read; counter->name = "Slice0 Subslice6 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice6 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler04_output_ready__read; counter->name = "Slice0 Subslice4 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice4 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler03_output_ready__read; counter->name = "Slice0 Subslice3 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice3 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 112; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__sampler_2__avg_gpu_core_frequency__max(perf); counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 128) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler07_output_ready__read; counter->name = "Slice0 Subslice7 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice7 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; if (perf->sys_vars.subslice_mask & 32) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler05_output_ready__read; counter->name = "Slice0 Subslice5 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice5 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 196; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler00_output_ready__read; counter->name = "Slice0 Subslice0 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__sampler_2__sampler01_output_ready__read; counter->name = "Slice0 Subslice1 Sampler Output Ready"; counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__sampler_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_tdl_1_mux_regs[186]; static struct gen_perf_query_register_prog icl_tdl_1_b_counter_regs[21]; static struct gen_perf_query_register_prog icl_tdl_1_flex_regs[7]; static struct gen_perf_query_counter icl_tdl_1_query_counters[51]; static struct gen_perf_query_info icl_tdl_1_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_1", .guid = "eddc2f32-b196-4a72-9bf8-21770e35f8bd", .counters = icl_tdl_1_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_tdl_1_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_tdl_1_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_tdl_1_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_tdl_1_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_tdl_1_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14A90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14AE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1E0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0429C300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062900C5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022EC300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042E00C5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A304000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C300001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5F000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C600014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16612800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0069C300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026900C5 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6A00F0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6EC5C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6FC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E700050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A9EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9E0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AA02A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CA00001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16A102A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CA9C5C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22A90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AAF000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AAA0005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18ACAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AAEC5C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10AE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AAFC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB05000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DE8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADE3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDF3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00E04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AE000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E10002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08E9C5C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EA0500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EE00C3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EEC500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EF4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CF00040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2406FF00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E08A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02082000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14090050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06091000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1812FC00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A12002B }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A13F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04136000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16152AD0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0418A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A198000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C19A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121D5400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141D0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F3000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F5030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F2020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F3030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F5050 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000018 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFC }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000060 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF3 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000180 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000600 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF3F }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00001800 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FCFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00006000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000F3FF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00018000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00060000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00003FFF }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread03_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice3 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__tdl_1__avg_gpu_core_frequency__max(perf); counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__ps_eu_stall_per_thread__read; counter->name = "FS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__vs_eu_stall_per_thread__read; counter->name = "VS AVG Stall per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__ps_eu_active_per_thread__read; counter->name = "FS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_eu_active__read; counter->name = "FS EU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 200; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread00_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 204; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; if (perf->sys_vars.subslice_mask & 128) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread07_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice7 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 220; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_eu_stall__read; counter->name = "FS EU Stall"; counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 244; if (perf->sys_vars.subslice_mask & 32) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread05_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice5 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 248; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__vs_eu_active__read; counter->name = "VS EU Active"; counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 252; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread01_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread04_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice4 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__vs_eu_stall__read; counter->name = "VS EU Stall"; counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__vs_eu_active_per_thread__read; counter->name = "VS AVG Active per Thread"; counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread02_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 312; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 328; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_1__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 336; if (perf->sys_vars.subslice_mask & 64) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_1__ps_thread06_ready_for_dispatch__read; counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher"; counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice6 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 344; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_tdl_2_mux_regs[127]; static struct gen_perf_query_register_prog icl_tdl_2_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_tdl_2_flex_regs[5]; static struct gen_perf_query_counter icl_tdl_2_query_counters[44]; static struct gen_perf_query_info icl_tdl_2_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_2", .guid = "c6d3af7b-037b-4656-95e1-4f838f0a2c14", .counters = icl_tdl_2_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_tdl_2_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_tdl_2_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_tdl_2_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_tdl_2_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_tdl_2_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14A90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14AE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1E0006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0006 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C200005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16210A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C29C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2A0034 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E00C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E300010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5E0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5F0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C600010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02604000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16612000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02618000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E69C100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6A0040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026AC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0008 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006EC100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A700400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04A04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06A04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04A18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06A18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02A900C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22A90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AAC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AEC100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10AE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AB04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DEC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08E04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04E900C1 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CE90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CEC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EEC100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CF00004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040150 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E040015 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050054 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04054000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600E0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24063E00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00088000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14090040 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04094000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A120020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02128000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0412C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0612C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A138000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413E000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0214C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16156000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150007 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1419000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1F3061 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F3050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3730 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__gt_request_queue_full__read; counter->name = "SQ is full"; counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread02_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 72; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread03_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice3 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice3 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__tdl_2__avg_gpu_core_frequency__max(perf); counter->offset = 120; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread00_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 136; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 164; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; if (perf->sys_vars.subslice_mask & 128) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread07_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice7 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice7 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 184; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 232; if (perf->sys_vars.subslice_mask & 64) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread06_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice6 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice6 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 240; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 256; if (perf->sys_vars.subslice_mask & 32) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread05_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice5 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice5 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 264; } if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread04_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice4 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice4 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 268; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 288; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_2__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 296; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_2__non_ps_thread01_ready_for_dispatch__read; counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher"; counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 304; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_tdl_3_mux_regs[191]; static struct gen_perf_query_register_prog icl_tdl_3_b_counter_regs[5]; static struct gen_perf_query_register_prog icl_tdl_3_flex_regs[5]; static struct gen_perf_query_counter icl_tdl_3_query_counters[51]; static struct gen_perf_query_info icl_tdl_3_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TDL_3", .guid = "fd25ec19-3ed1-40c9-8648-1d2387449a92", .counters = icl_tdl_3_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_tdl_3_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_tdl_3_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ .flex_regs = icl_tdl_3_flex_regs, .n_flex_regs = 0, /* Determined at runtime */ }; static void icl_register_tdl_3_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_tdl_3_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14292C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16290013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x142E2C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162E0013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14692C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16690013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146E2C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166E0013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14A92C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16A90013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14AE2C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AE0013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14E92C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E90013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EE2C00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EE0013 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1E3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F3800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2000A0 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16210002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002900C7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0629CF00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20290000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2A4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182A0F00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082ECFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082FC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C300500 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5EC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5E0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5FC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5F0003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A602A00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C600001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166102A8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A69CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22690000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186A5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6A000F }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186CAA00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6ECFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106E0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6FC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E700005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9E000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149E8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F000C }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CA00014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02A04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04A04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16A12800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02A18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04A18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EA9CFC7 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22A90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AAA0050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AAC000A }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08AC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AEC700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AE00CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10AE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AF4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AB01400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16DE8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DEC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADE0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDF0400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06E04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08E04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CE04000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08E18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CE18000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02E9C700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04E900CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22E90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CE90000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EA4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CEAC000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CEC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEC8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EEC700 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EE00CF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EE0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EF8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EF4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CF00014 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C045400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E045555 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10040155 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14050055 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08055000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2406FF00 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x260600FF }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A08A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C08A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E095000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14090005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080E5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1812A800 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A12003E }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0212C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0412C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A13F000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04136000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E14C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00148000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02144000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0015C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E15C000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16152AF8 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18150005 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04154000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C158000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00182000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06188000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0818A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08192000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E198000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190140 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1CA000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021C2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141D0028 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081D8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x521F4924 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0024 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2420 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3E1F5000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x461F3050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x481F2030 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4A1F0020 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F5050 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3030 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; query->flex_regs[query->n_flex_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__eu_active__read; counter->name = "EU Active"; counter->desc = "The percentage of time in which the Execution Units were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; if (perf->sys_vars.subslice_mask & 64) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header06_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice6 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 12; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__eu_fpu_both_active__read; counter->name = "EU Both FPU Pipes Active"; counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__vs_send_active__read; counter->name = "VS Send Pipe Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 20; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__vs_fpu1_active__read; counter->name = "VS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__gs_threads__read; counter->name = "GS Threads Dispatched"; counter->desc = "The total number of geometry shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__hi_depth_test_fails__read; counter->name = "Early Hi-Depth Test Fails"; counter->desc = "The total number of pixels dropped on early hierarchical depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__ps_eu_both_fpu_active__read; counter->name = "FS Both FPU Active"; counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__vs_threads__read; counter->name = "VS Threads Dispatched"; counter->desc = "The total number of vertex shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header03_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice3 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 64; } if (perf->sys_vars.subslice_mask & 8) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header03_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice3 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice3 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 68; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__ps_threads__read; counter->name = "FS Threads Dispatched"; counter->desc = "The total number of fragment shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header04_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice4 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 80; } if (perf->sys_vars.subslice_mask & 16) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header04_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice4 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice4 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 84; } if (perf->sys_vars.subslice_mask & 64) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header06_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice6 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice6 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 88; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__shader_barriers__read; counter->name = "Shader Barrier Messages"; counter->desc = "The total number of shader barrier messages."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 96; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__sampler_texels__read; counter->name = "Sampler Texels"; counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 104; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__pixels_failing_post_ps_tests__read; counter->name = "Pixels Failing Tests"; counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 112; if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header01_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 120; } if (perf->sys_vars.subslice_mask & 2) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header01_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 124; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 128; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__tdl_3__avg_gpu_core_frequency__max(perf); counter->offset = 136; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__sampler_texel_misses__read; counter->name = "Sampler Texels Misses"; counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 144; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__cs_threads__read; counter->name = "CS Threads Dispatched"; counter->desc = "The total number of compute shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 152; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__slm_bytes_read__read; counter->name = "SLM Bytes Read"; counter->desc = "The total number of GPU memory bytes read from shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 160; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__ps_fpu1_active__read; counter->name = "PS FPU1 Pipe Active"; counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 168; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__ps_send_active__read; counter->name = "PS Send Pipeline Active"; counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 172; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__vs_fpu0_active__read; counter->name = "VS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 176; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 180; if (perf->sys_vars.subslice_mask & 128) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header07_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice7 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 184; } if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header02_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 188; } if (perf->sys_vars.subslice_mask & 4) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header02_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 192; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__rasterized_pixels__read; counter->name = "Rasterized Pixels"; counter->desc = "The total number of rasterized pixels."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 200; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__ps_fpu0_active__read; counter->name = "PS FPU0 Pipe Active"; counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 208; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__ds_threads__read; counter->name = "DS Threads Dispatched"; counter->desc = "The total number of domain shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 216; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__samples_written__read; counter->name = "Samples Written"; counter->desc = "The total number of samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 224; if (perf->sys_vars.subslice_mask & 32) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header05_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice5 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 232; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__eu_stall__read; counter->name = "EU Stall"; counter->desc = "The percentage of time in which the Execution Units were stalled."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 236; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__samples_blended__read; counter->name = "Samples Blended"; counter->desc = "The total number of blended samples or pixels written to all render targets."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 240; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__early_depth_test_fails__read; counter->name = "Early Depth Test Fails"; counter->desc = "The total number of pixels dropped on early depth test."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 248; if (perf->sys_vars.subslice_mask & 128) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header07_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice7 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice7 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 256; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__shader_memory_accesses__read; counter->name = "Shader Memory Accesses"; counter->desc = "The total number of shader memory accesses to L3."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 264; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__hs_threads__read; counter->name = "HS Threads Dispatched"; counter->desc = "The total number of hull shader hardware threads dispatched."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 272; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__l3_shader_throughput__read; counter->name = "L3 Shader Throughput"; counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 280; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__samples_killed_in_ps__read; counter->name = "Samples Killed in FS"; counter->desc = "The total number of samples or pixels dropped in fragment shaders."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 288; if (perf->sys_vars.subslice_mask & 32) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header05_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice5 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice5 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 296; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__slm_bytes_written__read; counter->name = "SLM Bytes Written"; counter->desc = "The total number of GPU memory bytes written into shared local memory."; counter->type = GEN_PERF_COUNTER_TYPE_THROUGHPUT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* unsupported (varies over time) */; counter->offset = 304; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header00_ready_port0__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 312; } counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__tdl_3__shader_atomics__read; counter->name = "Shader Atomic Memory Accesses"; counter->desc = "The total number of shader atomic memory accesses."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 320; if (perf->sys_vars.subslice_mask & 1) { counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__tdl_3__thread_header00_ready_port1__read; counter->name = "Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1"; counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 328; } query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_gpu_busyness_mux_regs[55]; static struct gen_perf_query_register_prog icl_gpu_busyness_b_counter_regs[7]; static struct gen_perf_query_counter icl_gpu_busyness_query_counters[11]; static struct gen_perf_query_info icl_gpu_busyness_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Gpu Rings Busyness", .guid = "40dc79f2-88c8-47c6-8f86-f509e39fbe5d", .counters = icl_gpu_busyness_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_gpu_busyness_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_gpu_busyness_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void icl_register_gpu_busyness_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_gpu_busyness_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E061200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22062400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10002400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00038000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06032000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020600F3 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C060043 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20060000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02000023 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x20002000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3A1F6000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4E1F2900 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x501F00E9 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10204000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C214000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x401F4131 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x421F1021 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x441F3100 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000002 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181B2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B2400 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12240120 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06218000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08212000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180B8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040F8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E080010 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8300 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x221B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041E4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084A8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184B4000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F2000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E480004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B0083 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x225B0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045E1000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0823A000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02242980 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10240000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06240000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A244000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C250004 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08268000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__gpu_busyness__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__vebox_busy__read; counter->name = "Vebox Ring Busy"; counter->desc = "The percentage of time when vebox command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__gpu_busyness__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__gpu_busyness__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__gpu_busyness__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__render_busy__read; counter->name = "Render Ring Busy"; counter->desc = "The percentage of time when render command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__vdbox0_busy__read; counter->name = "Vdbox0 Ring Busy"; counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 36; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__posh_engine_busy__read; counter->name = "Posh Ring Busy"; counter->desc = "The percentage of time when posh command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__blitter_busy__read; counter->name = "Blitter Ring Busy"; counter->desc = "The percentage of time when blitter command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 44; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__vdbox1_busy__read; counter->name = "Vdbox1 Ring Busy"; counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__any_ring_busy__read; counter->name = "AnyRingBusy"; counter->desc = "The percentage of time when any command streamer was busy."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 52; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_float = icl__gpu_busyness__gpu_busy__read; counter->name = "GPU Busy"; counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_FLOAT; counter->raw_max = 100.0; counter->offset = 56; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } static struct gen_perf_query_register_prog icl_test_oa_mux_regs[12]; static struct gen_perf_query_register_prog icl_test_oa_b_counter_regs[21]; static struct gen_perf_query_counter icl_test_oa_query_counters[12]; static struct gen_perf_query_info icl_test_oa_query = { .kind = GEN_PERF_QUERY_TYPE_OA, .name = "Metric set TestOa", .guid = "3c0bf614-5d67-4326-887f-a24eb8a58244", .counters = icl_test_oa_query_counters, .n_counters = 0, .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, /* Accumulation buffer offsets... */ .gpu_time_offset = 0, .gpu_clock_offset = 1, .a_offset = 2, .b_offset = 38, .c_offset = 46, .mux_regs = icl_test_oa_mux_regs, .n_mux_regs = 0, /* Determined at runtime */ .b_counter_regs = icl_test_oa_b_counter_regs, .n_b_counter_regs = 0, /* Determined at runtime */ }; static void icl_register_test_oa_counter_query(struct gen_perf *perf) { static struct gen_perf_query_info *query = &icl_test_oa_query; struct gen_perf_query_counter *counter; /* Note: we're assuming there can't be any variation in the definition * of a query between contexts so it's ok to describe a query within a * global variable which only needs to be initialized once... */ if (!query->data_size) { query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000003 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24000001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E130056 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A130000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x541F0001 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4C1F0000 }; query->mux_regs[query->n_mux_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00009888, .val = 0x301F0000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFFF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; query->b_counter_regs[query->n_b_counter_regs++] = (struct gen_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter7__read; counter->name = "TestCounter7"; counter->desc = "HW test counter 7. Factor: 0.6666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 0; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__gpu_time__read; counter->name = "GPU Time Elapsed"; counter->desc = "Time elapsed on the GPU during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_RAW; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 8; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__gpu_core_clocks__read; counter->name = "GPU Core Clocks"; counter->desc = "The total number of GPU core clocks elapsed during the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 16; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__avg_gpu_core_frequency__read; counter->name = "AVG GPU Core Frequency"; counter->desc = "Average GPU Core Frequency in the measurement."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = icl__test_oa__avg_gpu_core_frequency__max(perf); counter->offset = 24; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter8__read; counter->name = "TestCounter8"; counter->desc = "HW test counter 8. Should be equal to 1."; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 32; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter4__read; counter->name = "TestCounter4"; counter->desc = "HW test counter 4. Factor: 0.3333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 40; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter5__read; counter->name = "TestCounter5"; counter->desc = "HW test counter 5. Factor: 0.3333"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 48; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter6__read; counter->name = "TestCounter6"; counter->desc = "HW test counter 6. Factor: 0.16666"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 56; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter3__read; counter->name = "TestCounter3"; counter->desc = "HW test counter 3. Factor: 0.5"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 64; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter0__read; counter->name = "TestCounter0"; counter->desc = "HW test counter 0. Factor: 0.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 72; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter1__read; counter->name = "TestCounter1"; counter->desc = "HW test counter 1. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 80; counter = &query->counters[query->n_counters++]; counter->oa_counter_read_uint64 = icl__test_oa__counter2__read; counter->name = "TestCounter2"; counter->desc = "HW test counter 2. Factor: 1.0"; counter->type = GEN_PERF_COUNTER_TYPE_EVENT; counter->data_type = GEN_PERF_COUNTER_DATA_TYPE_UINT64; counter->raw_max = 0 /* undefined */; counter->offset = 88; query->data_size = counter->offset + gen_perf_query_counter_get_size(counter); } _mesa_hash_table_insert(perf->oa_metrics_table, query->guid, query); } void gen_oa_register_queries_icl(struct gen_perf *perf) { icl_register_render_basic_counter_query(perf); icl_register_compute_basic_counter_query(perf); icl_register_compute_extended_counter_query(perf); icl_register_compute_l3_cache_counter_query(perf); icl_register_render_pipe_profile_counter_query(perf); icl_register_hdc_and_sf_counter_query(perf); icl_register_rasterizer_and_pixel_backend_counter_query(perf); icl_register_l3_1_counter_query(perf); icl_register_l3_2_counter_query(perf); icl_register_l3_3_counter_query(perf); icl_register_l3_4_counter_query(perf); icl_register_l3_5_counter_query(perf); icl_register_sampler_1_counter_query(perf); icl_register_sampler_2_counter_query(perf); icl_register_tdl_1_counter_query(perf); icl_register_tdl_2_counter_query(perf); icl_register_tdl_3_counter_query(perf); icl_register_gpu_busyness_counter_query(perf); icl_register_test_oa_counter_query(perf); }